CLKMGR Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.560s	302.161us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.040s	122.535us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.410s	523.237us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	3.030s	689.551us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.800s	97.814us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	689.551us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.020s	125.556us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.270s	169.509us	50	50	100.00
V2	extclk	clkmgr_extclk	2.020s	452.959us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.090s	182.961us	50	50	100.00
V2	jitter	clkmgr_smoke	1.560s	302.161us	50	50	100.00
V2	frequency	clkmgr_frequency	17.790s	2.358ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.150s	2.295ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.790s	2.358ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.639m	14.770ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.800s	78.186us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.170s	172.983us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.320s	934.050us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.320s	934.050us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.040s	122.535us	5	5	100.00
		clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	689.551us	5	5	100.00
		clkmgr_same_csr_outstanding	1.640s	194.018us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.040s	122.535us	5	5	100.00
		clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	689.551us	5	5	100.00
		clkmgr_same_csr_outstanding	1.640s	194.018us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.170s	908.550us	5	5	100.00
		clkmgr_tl_intg_err	3.660s	452.371us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.910s	452.023us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.910s	452.023us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.910s	452.023us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.910s	452.023us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.650s	673.431us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.660s	452.371us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.790s	2.358ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.150s	2.295ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.910s	452.023us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.800s	314.037us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.230s	153.044us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.730s	370.574us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.100s	84.154us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.300s	189.879us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.170s	908.550us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.960s	65.092us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.170s	908.550us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	36.023m	654.312ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			960	960	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.12	95.44	100.00	100.00	98.71	96.97	93.18

Past Results

• Latest
• 2023.05.19_16.00.06
• 2023.05.18_19.04.30
• 2023.05.17_17.46.49
• 2023.05.16_19.12.30
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• 2023.05.14_17.56.25
• 2023.05.13_18.39.16