042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 1.480s | 257.970us | 32 | 50 | 64.00 |
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0.900s | 63.005us | 4 | 5 | 80.00 |
| V1 | csr_rw | clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 |
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 10.280s | 3.024ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | clkmgr_csr_aliasing | 1.590s | 101.846us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 1.820s | 108.071us | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 |
| clkmgr_csr_aliasing | 1.590s | 101.846us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 72 | 105 | 68.57 | |||
| V2 | peri_enables | clkmgr_peri | 1.150s | 156.080us | 40 | 50 | 80.00 |
| V2 | trans_enables | clkmgr_trans | 1.430s | 207.024us | 37 | 50 | 74.00 |
| V2 | extclk | clkmgr_extclk | 1.250s | 196.473us | 41 | 50 | 82.00 |
| V2 | clk_status | clkmgr_clk_status | 0.850s | 59.943us | 43 | 50 | 86.00 |
| V2 | jitter | clkmgr_smoke | 1.480s | 257.970us | 32 | 50 | 64.00 |
| V2 | frequency | clkmgr_frequency | 18.350s | 2.480ms | 39 | 50 | 78.00 |
| V2 | frequency_timeout | clkmgr_frequency_timeout | 15.830s | 2.179ms | 46 | 50 | 92.00 |
| V2 | frequency_overflow | clkmgr_frequency | 18.350s | 2.480ms | 39 | 50 | 78.00 |
| V2 | stress_all | clkmgr_stress_all | 1.024m | 8.392ms | 41 | 50 | 82.00 |
| V2 | intr_test | clkmgr_intr_test | 0.800s | 16.010us | 45 | 50 | 90.00 |
| V2 | alert_test | clkmgr_alert_test | 1.120s | 159.090us | 34 | 50 | 68.00 |
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 4.830s | 579.273us | 14 | 20 | 70.00 |
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 4.830s | 579.273us | 14 | 20 | 70.00 |
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0.900s | 63.005us | 4 | 5 | 80.00 |
| clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 | ||
| clkmgr_csr_aliasing | 1.590s | 101.846us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 1.310s | 86.559us | 16 | 20 | 80.00 | ||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0.900s | 63.005us | 4 | 5 | 80.00 |
| clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 | ||
| clkmgr_csr_aliasing | 1.590s | 101.846us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 1.310s | 86.559us | 16 | 20 | 80.00 | ||
| V2 | TOTAL | 396 | 490 | 80.82 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 2.450s | 367.605us | 4 | 5 | 80.00 |
| clkmgr_tl_intg_err | 4.330s | 1.218ms | 18 | 20 | 90.00 | ||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 3.240s | 747.861us | 16 | 20 | 80.00 |
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 3.240s | 747.861us | 16 | 20 | 80.00 |
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 3.240s | 747.861us | 16 | 20 | 80.00 |
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 3.240s | 747.861us | 16 | 20 | 80.00 |
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 3.900s | 856.813us | 16 | 20 | 80.00 |
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 4.330s | 1.218ms | 18 | 20 | 90.00 |
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 18.350s | 2.480ms | 39 | 50 | 78.00 |
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 15.830s | 2.179ms | 46 | 50 | 92.00 |
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 3.240s | 747.861us | 16 | 20 | 80.00 |
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 1.370s | 186.497us | 38 | 50 | 76.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 1.430s | 251.806us | 37 | 50 | 74.00 |
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 1.010s | 90.940us | 37 | 50 | 74.00 |
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 1.380s | 209.276us | 37 | 50 | 74.00 |
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 1.600s | 287.022us | 39 | 50 | 78.00 |
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 |
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 2.450s | 367.605us | 4 | 5 | 80.00 |
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 |
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0.960s | 57.219us | 13 | 20 | 65.00 |
| V2S | prim_count_check | clkmgr_sec_cm | 2.450s | 367.605us | 4 | 5 | 80.00 |
| V2S | TOTAL | 242 | 315 | 76.83 | |||
| V3 | regwen | clkmgr_regwen | 5.820s | 1.039ms | 43 | 50 | 86.00 |
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 48.592m | 786.290ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 86 | 100 | 86.00 | |||
| TOTAL | 796 | 1010 | 78.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 1 | 16.67 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.53 | 99.15 | 95.76 | 100.00 | 100.00 | 98.81 | 97.01 | 98.97 |
Exit reason: Error: User command failed Job returned non-zero exit code has 193 failures:
Test clkmgr_lc_clk_byp_req_intersig_mubi has 12 failures.
0.clkmgr_lc_clk_byp_req_intersig_mubi.103659524242881786908591768699263731457034721590185728670940744675281418539534
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest && /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608995342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.1608995342
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.clkmgr_lc_clk_byp_req_intersig_mubi.105052036744528088501935250595855710936489892569799068080039871556358198091360
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest && /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173891168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.173891168
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 10 more failures.
Test clkmgr_regwen has 5 failures.
0.clkmgr_regwen.310323117428393868845052407905030368335221318486129873417077517057255202756
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log
[make]: simulate
cd /workspace/0.clkmgr_regwen/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077862340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1077862340
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.clkmgr_regwen.95751049335339613040325244142976868814416697060053487162361781572355178761799
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_regwen/latest/run.log
[make]: simulate
cd /workspace/9.clkmgr_regwen/latest && /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237350983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3237350983
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test clkmgr_tl_errors has 6 failures.
0.clkmgr_tl_errors.96672475186780528520318555793145369217342186779423100301062997335138757419202
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest/run.log
[make]: simulate
cd /workspace/0.clkmgr_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482938050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2482938050
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.clkmgr_tl_errors.39473981210109488752779016772595189936792876981502546115826161389249241969425
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest/run.log
[make]: simulate
cd /workspace/3.clkmgr_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948939025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.1948939025
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:24 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
Test clkmgr_csr_hw_reset has 1 failures.
0.clkmgr_csr_hw_reset.21029699871378943626046382531577038852882882382637196002077075665515543070497
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/0.clkmgr_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523544865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.3523544865
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_csr_rw has 7 failures.
0.clkmgr_csr_rw.69746584040101454424505498639290550940658325466296243311421863900149646704704
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log
[make]: simulate
cd /workspace/0.clkmgr_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871186496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.871186496
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.clkmgr_csr_rw.77792991835363472766047879693085865691044397477309617610891156532919380860179
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest/run.log
[make]: simulate
cd /workspace/3.clkmgr_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265649939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.3265649939
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
... and 21 more tests.
Job clkmgr-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
Test clkmgr_smoke has 3 failures.
0.clkmgr_smoke.98798825025299770632627867567499842320309157165739610442130846836074738846367
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest/run.log
Job ID: smart:2923244e-9f63-47cb-8d3f-7379c44c2104
9.clkmgr_smoke.111373438299538991652066096402463292527311276152250124977558953692745285958981
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_smoke/latest/run.log
Job ID: smart:27e140d2-c2e3-4cf7-9217-a3da4b59c7d3
... and 1 more failures.
Test clkmgr_sec_cm has 1 failures.
0.clkmgr_sec_cm.43739823764221061350561853184058486030210192949585186500914423390774051371982
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log
Job ID: smart:062b26e8-c732-4474-a72a-c1d406f1af6c
Test clkmgr_frequency has 2 failures.
7.clkmgr_frequency.78126986303068154806672596939410085964809721542919823413716232518193537271273
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_frequency/latest/run.log
Job ID: smart:3f03ec05-6778-437b-82c1-4efefe9713ea
18.clkmgr_frequency.111444820570397488242222779677906166712730215637647258037164826485949290209798
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_frequency/latest/run.log
Job ID: smart:af3c1049-9c7c-4060-a1a4-446a64df8678
Test clkmgr_trans has 1 failures.
7.clkmgr_trans.8351480379991677115222090348558322247810844240749934031014341655132239380029
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_trans/latest/run.log
Job ID: smart:8bc72f39-088a-4e04-8f5c-e5efa6048d8d
Test clkmgr_alert_test has 1 failures.
14.clkmgr_alert_test.107548460846110809757362520088938611070134626444225987641857880871137557169374
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_alert_test/latest/run.log
Job ID: smart:17503417-cb37-4d1c-a26b-640a3b7b2c78
... and 6 more tests.
Job clkmgr-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test clkmgr_same_csr_outstanding has 1 failures.
11.clkmgr_same_csr_outstanding.43968140618277776651391686641583195639250935476952035966626315642099479545664
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest/run.log
Job ID: smart:77af2648-d21e-4573-90da-b6bc7e7e5e66
Test clkmgr_intr_test has 1 failures.
15.clkmgr_intr_test.98034441838063841105335068936526354377545698022607366349845405292444720797482
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_intr_test/latest/run.log
Job ID: smart:a67be990-80cd-4e20-844a-2b1a3f8a9278
Test clkmgr_tl_intg_err has 1 failures.
16.clkmgr_tl_intg_err.109366592787895978866049828609961912216992079825070261773070923171672279622577
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest/run.log
Job ID: smart:f91706b5-05e7-41d5-b671-00e62f389950
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:
21.clkmgr_stress_all_with_rand_reset.54852609980192351805616618178374499785086990073490049945080752665273094047605
Line 343, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
UVM_ERROR @ 5445398555 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
UVM_INFO @ 5445398555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---