cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 1.320s | 189.677us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 1.300s | 233.245us | 5 | 5 | 100.00 |
| V1 | csr_rw | clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 9.080s | 991.160us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | clkmgr_csr_aliasing | 2.050s | 211.619us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 2.080s | 399.778us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 |
| clkmgr_csr_aliasing | 2.050s | 211.619us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | peri_enables | clkmgr_peri | 1.140s | 157.003us | 49 | 50 | 98.00 |
| V2 | trans_enables | clkmgr_trans | 2.300s | 513.079us | 50 | 50 | 100.00 |
| V2 | extclk | clkmgr_extclk | 1.550s | 249.840us | 50 | 50 | 100.00 |
| V2 | clk_status | clkmgr_clk_status | 0.830s | 73.458us | 50 | 50 | 100.00 |
| V2 | jitter | clkmgr_smoke | 1.320s | 189.677us | 50 | 50 | 100.00 |
| V2 | frequency | clkmgr_frequency | 18.960s | 2.474ms | 50 | 50 | 100.00 |
| V2 | frequency_timeout | clkmgr_frequency_timeout | 17.430s | 2.420ms | 50 | 50 | 100.00 |
| V2 | frequency_overflow | clkmgr_frequency | 18.960s | 2.474ms | 50 | 50 | 100.00 |
| V2 | stress_all | clkmgr_stress_all | 1.193m | 11.894ms | 50 | 50 | 100.00 |
| V2 | intr_test | clkmgr_intr_test | 0.900s | 125.014us | 43 | 50 | 86.00 |
| V2 | alert_test | clkmgr_alert_test | 1.110s | 157.752us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 4.990s | 1.171ms | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 4.990s | 1.171ms | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 1.300s | 233.245us | 5 | 5 | 100.00 |
| clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 | ||
| clkmgr_csr_aliasing | 2.050s | 211.619us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 2.890s | 684.923us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 1.300s | 233.245us | 5 | 5 | 100.00 |
| clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 | ||
| clkmgr_csr_aliasing | 2.050s | 211.619us | 5 | 5 | 100.00 | ||
| clkmgr_same_csr_outstanding | 2.890s | 684.923us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 481 | 490 | 98.16 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 3.380s | 321.311us | 5 | 5 | 100.00 |
| clkmgr_tl_intg_err | 4.270s | 1.117ms | 19 | 20 | 95.00 | ||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 4.320s | 1.114ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 4.320s | 1.114ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 4.320s | 1.114ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 4.320s | 1.114ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 4.200s | 491.260us | 18 | 20 | 90.00 |
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 4.270s | 1.117ms | 19 | 20 | 95.00 |
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 18.960s | 2.474ms | 50 | 50 | 100.00 |
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 17.430s | 2.420ms | 50 | 50 | 100.00 |
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 4.320s | 1.114ms | 20 | 20 | 100.00 |
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 1.840s | 328.321us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 1.680s | 331.602us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 1.550s | 272.142us | 50 | 50 | 100.00 |
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 1.960s | 328.303us | 50 | 50 | 100.00 |
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 1.240s | 155.171us | 50 | 50 | 100.00 |
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 |
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 3.380s | 321.311us | 5 | 5 | 100.00 |
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 |
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 1.140s | 177.893us | 20 | 20 | 100.00 |
| V2S | prim_count_check | clkmgr_sec_cm | 3.380s | 321.311us | 5 | 5 | 100.00 |
| V2S | TOTAL | 312 | 315 | 99.05 | |||
| V3 | regwen | clkmgr_regwen | 7.770s | 1.322ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 30.558m | 452.383ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 100 | 100 | 100.00 | |||
| TOTAL | 998 | 1010 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 11 | 11 | 8 | 72.73 |
| V2S | 9 | 9 | 7 | 77.78 |
| V3 | 2 | 2 | 2 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.54 | 99.15 | 95.84 | 100.00 | 100.00 | 98.81 | 97.01 | 98.97 |
Exit reason: Error: User command failed Job returned non-zero exit code has 11 failures:
Test clkmgr_shadow_reg_errors_with_csr_rw has 2 failures.
7.clkmgr_shadow_reg_errors_with_csr_rw.106590606406944548701500726401285134752986826187125481492518304703052760073713
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log
[make]: simulate
cd /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271228401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.4271228401
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
15.clkmgr_shadow_reg_errors_with_csr_rw.7678806569090624425630799442517646162877431224584708018593693249446619707206
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log
[make]: simulate
cd /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362060102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3362060102
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_tl_intg_err has 1 failures.
7.clkmgr_tl_intg_err.54056395552279385943593814278006750141429701646085252417429660288849880760557
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/7.clkmgr_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327106797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.327106797
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_tl_errors has 1 failures.
8.clkmgr_tl_errors.10000631674752516600884715627950467432245197730327822748853287965347835019476
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest/run.log
[make]: simulate
cd /workspace/8.clkmgr_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393033428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.1393033428
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test clkmgr_intr_test has 7 failures.
36.clkmgr_intr_test.85432394299544589543542729876606601353366667974120776386355023938201084168798
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_intr_test/latest/run.log
[make]: simulate
cd /workspace/36.clkmgr_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642427998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.3642427998
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
38.clkmgr_intr_test.25672615079118193354423063582889779020445979734137857104574485033403206323951
Log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_intr_test/latest/run.log
[make]: simulate
cd /workspace/38.clkmgr_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666333423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.3666333423
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:
28.clkmgr_peri.37212293032095564345310988608737887730955806563072827822273969528728893732701
Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_peri/latest/run.log
Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
UVM_ERROR @ 3212354 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
UVM_INFO @ 3212354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---