CSRNG Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	24.522us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	19.600us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	24.991us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	25.000s	1.238ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	38.969us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	99.200us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	24.991us	20	20	100.00
		csrng_csr_aliasing	4.000s	38.969us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	198.521us	200	200	100.00
V2	alerts	csrng_alert	8.000s	508.000us	500	500	100.00
V2	err	csrng_err	6.000s	20.660us	487	500	97.40
V2	cmds	csrng_cmds	1.150m	5.528ms	50	50	100.00
V2	life cycle	csrng_cmds	1.150m	5.528ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.867m	9.184ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	88.632us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	57.058us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	1.173ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	1.173ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	19.600us	5	5	100.00
		csrng_csr_rw	5.000s	24.991us	20	20	100.00
		csrng_csr_aliasing	4.000s	38.969us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	271.509us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	19.600us	5	5	100.00
		csrng_csr_rw	5.000s	24.991us	20	20	100.00
		csrng_csr_aliasing	4.000s	38.969us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	271.509us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	8.000s	692.640us	5	5	100.00
		csrng_tl_intg_err	9.000s	367.244us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	125.379us	50	50	100.00
		csrng_csr_rw	5.000s	24.991us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	508.000us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.867m	9.184ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	508.000us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.867m	9.184ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	508.000us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	367.244us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
		csrng_sec_cm	8.000s	692.640us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	198.521us	200	200	100.00
		csrng_err	6.000s	20.660us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	51.533m	50.799ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			1610	1670	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.84	93.35	84.31	95.43	86.47	92.29	100.00	97.50	95.17

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 28 failures:
- Test csrng_stress_all_with_rand_reset has 28 failures.
  - 0.csrng_stress_all_with_rand_reset.1447470050
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10002544266 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x8827314) == 0x6
  UVM_INFO @ 10002544266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.2825926138
    Line 262, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10001634414 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xb079ba94) == 0x6
  UVM_INFO @ 10001634414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 12 failures:
- Test csrng_stress_all_with_rand_reset has 12 failures.
  - 1.csrng_stress_all_with_rand_reset.2856041553
    Line 490, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19041256259 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x2844214) == 0x6
  UVM_INFO @ 19041256259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.529019846
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15224895424 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x2a0dfc14) == 0x6
  UVM_INFO @ 15224895424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

42.csrng_err.3393953038
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 29607891 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  29607891 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  29607891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.csrng_err.3048172808
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/51.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1901534 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1901534 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1901534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

177.csrng_err.3952841174
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/177.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  177.csrng_err.3952841174
  
  coverage files:
    model(design data) :  /workspace/coverage/default/177.csrng_err.3952841174/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/177.csrng_err.3952841174/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 21, 2023 at 00:45:43 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1

421.csrng_err.2698635160
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/421.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  421.csrng_err.2698635160
  
  coverage files:
    model(design data) :  /workspace/coverage/default/421.csrng_err.2698635160/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/421.csrng_err.2698635160/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 21, 2023 at 00:47:42 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 6.csrng_stress_all_with_rand_reset.2708483894
    Line 433, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14560592693 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 14560592693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.csrng_stress_all_with_rand_reset.1097816200
    Line 509, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28245308296 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 28245308296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

10.csrng_stress_all.3873811719
Line 262, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log

  UVM_ERROR @ 133635440 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 133635440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.csrng_stress_all.770094491
Line 253, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log

  UVM_ERROR @  18057843 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  18057843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

13.csrng_stress_all_with_rand_reset.2102320867
Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 9244028119 PS + 13
  Verilog Stack Trace:

31.csrng_stress_all_with_rand_reset.1445498238
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 26060589 PS + 14
  Verilog Stack Trace:

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

87.csrng_err.4215812322
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3335935 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3335935 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3335935 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3335935 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3335935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

457.csrng_err.2609854291
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/457.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 14601893 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 14601893 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 14601893 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  14601893 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  14601893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 2.csrng_stress_all_with_rand_reset.3392809313
    Line 242, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 798153761 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @ 798153761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 168.csrng_err.4269307817
    Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/168.csrng_err/latest/run.log
```
  UVM_ERROR @   8826588 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   8826588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```