CSRNG Simulation Results

Sunday October 08 2023 19:02:39 UTC

GitHub Revision: `4e80560e2`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3527490040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	133.656us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	35.623us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	66.446us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	1.409ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	133.641us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	43.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	66.446us	20	20	100.00
		csrng_csr_aliasing	6.000s	133.641us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	8.000s	31.578us	200	200	100.00
V2	alerts	csrng_alert	10.000s	506.178us	500	500	100.00
V2	err	csrng_err	8.000s	20.510us	485	500	97.00
V2	cmds	csrng_cmds	11.567m	69.826ms	50	50	100.00
V2	life cycle	csrng_cmds	11.567m	69.826ms	50	50	100.00
V2	stress_all	csrng_stress_all	23.900m	134.684ms	49	50	98.00
V2	intr_test	csrng_intr_test	5.000s	65.798us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	20.565us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	1.209ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	1.209ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	35.623us	5	5	100.00
		csrng_csr_rw	6.000s	66.446us	20	20	100.00
		csrng_csr_aliasing	6.000s	133.641us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	67.824us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	35.623us	5	5	100.00
		csrng_csr_rw	6.000s	66.446us	20	20	100.00
		csrng_csr_aliasing	6.000s	133.641us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	67.824us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	6.000s	70.761us	5	5	100.00
		csrng_tl_intg_err	12.000s	1.331ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	10.000s	145.995us	50	50	100.00
		csrng_csr_rw	6.000s	66.446us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	506.178us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.900m	134.684ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	506.178us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.900m	134.684ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	506.178us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	1.331ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
		csrng_sec_cm	6.000s	70.761us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	8.000s	31.578us	200	200	100.00
		csrng_err	8.000s	20.510us	485	500	97.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.782h	96.035ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1634	1670	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.77	93.24	84.31	95.35	86.47	92.29	100.00	97.50	95.40

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

13.csrng_err.3374592375
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4197880 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4197880 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4197880 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4197880 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4197880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

22.csrng_err.552865414
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1911251 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1911251 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1911251 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1911251 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1911251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.2285202151
    Line 769, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 38368366470 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 38368366470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.csrng_stress_all_with_rand_reset.249659325
    Line 566, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 136606139642 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 136606139642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 8 failures:

Test csrng_stress_all_with_rand_reset has 8 failures.

7.csrng_stress_all_with_rand_reset.1529255903
Line 467, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 26906094932 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 26906094932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.csrng_stress_all_with_rand_reset.1989779845
Line 544, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 149670862909 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 149670862909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

97.csrng_err.1029035745
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/97.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1590698 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1590698 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1590698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

100.csrng_err.2004752494
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/100.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 23353447 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  23353447 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  23353447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

4.csrng_stress_all_with_rand_reset.2572423167
Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 12666504756 PS + 13
  Verilog Stack Trace:

12.csrng_stress_all_with_rand_reset.53946580
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 18370242 PS + 13
  Verilog Stack Trace:

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 14.csrng_stress_all_with_rand_reset.496894957
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:23ef5e58-dc29-4200-985e-c98dc35903f2
```
  - 42.csrng_stress_all_with_rand_reset.2995472767
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:7633f6e1-9eff-4e96-8a56-84195a36099d
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 23.csrng_stress_all.206130136
    Line 278, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6605439730 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6605439730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```