CSRNG Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	22.828us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	37.009us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	23.912us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	1.381ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	172.216us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	44.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	23.912us	20	20	100.00
		csrng_csr_aliasing	5.000s	172.216us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	75.842us	200	200	100.00
V2	alerts	csrng_alert	14.000s	57.516us	500	500	100.00
V2	err	csrng_err	10.000s	22.592us	489	500	97.80
V2	cmds	csrng_cmds	4.983m	13.115ms	50	50	100.00
V2	life cycle	csrng_cmds	4.983m	13.115ms	50	50	100.00
V2	stress_all	csrng_stress_all	16.883m	82.484ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	16.829us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	35.989us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	288.282us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	288.282us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	37.009us	5	5	100.00
		csrng_csr_rw	8.000s	23.912us	20	20	100.00
		csrng_csr_aliasing	5.000s	172.216us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	24.041us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	37.009us	5	5	100.00
		csrng_csr_rw	8.000s	23.912us	20	20	100.00
		csrng_csr_aliasing	5.000s	172.216us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	24.041us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	9.000s	798.619us	5	5	100.00
		csrng_tl_intg_err	32.000s	1.144ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	95.872us	50	50	100.00
		csrng_csr_rw	8.000s	23.912us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	14.000s	57.516us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	16.883m	82.484ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	14.000s	57.516us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	16.883m	82.484ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	14.000s	57.516us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	32.000s	1.144ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
		csrng_sec_cm	9.000s	798.619us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	75.842us	200	200	100.00
		csrng_err	10.000s	22.592us	489	500	97.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.839h	549.913ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1646	1670	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.70	93.18	84.17	95.30	86.34	92.23	100.00	97.33	95.29

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 7.csrng_stress_all_with_rand_reset.24504956764839666773686966677942491392603598706924920036801305379691536412334
    Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 21619064553 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 21619064553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.csrng_stress_all_with_rand_reset.81278324229028294894710177465718896800593989103018634527458864637307068318938
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 36537773594 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 36537773594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

42.csrng_err.76527029350474473140088308811390084305282848903883527554994857774845710943644
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 8943046 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8943046 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8943046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

116.csrng_err.2614839933994370846190036365165444914390576706372003644852815439281400783786
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3677017 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3677017 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3677017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

233.csrng_err.45317657544071049559450726885412542368128702951601008336167230516351257396632
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/233.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1967999 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1967999 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1967999 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1967999 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1967999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

251.csrng_err.90194147529387554935677958206264236549327209651457492295728730907449920201592
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/251.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1711417 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1711417 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1711417 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1711417 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1711417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 5.csrng_stress_all_with_rand_reset.103765669704737826642712305641300225220244359220594264404563966078686303066863
    Line 514, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 29145517090 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 29145517090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.csrng_stress_all_with_rand_reset.113299314361435576507873672566272974270584473617839953427649236397447812189318
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2000837926 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 2000837926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 9.csrng_stress_all_with_rand_reset.101475737762503923101445272544789019457160190395507436993176080512061259377162
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:43457744-ca25-4168-8b0d-8f434f52eb7c
```
  - 49.csrng_stress_all_with_rand_reset.48745093296552717964216246445564250843678304305986161738083891446158667561642
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/49.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:55295d3f-ca4f-4e9e-9836-c1d28c16e27c
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 0.csrng_stress_all.18134845703098473734335688380872495120977052294939726810859258468085805586596
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4623103616 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4623103616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.68243442041517564099406041497932666329796168966245426296447868189638979444320
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  36021722 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  36021722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 10.csrng_stress_all_with_rand_reset.97551280473830841923971023833402052449385724776784122482833739957877770444659
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6736986709 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @ 6736986709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 308.csrng_err.46262247167065816445658243310512775881104161750372258394955153280228868484467
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/308.csrng_err/latest/run.log
```
  UVM_ERROR @   9184161 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   9184161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```