CSRNG Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	22.375us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	228.041us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	43.923us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	345.935us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	822.186us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	13.000s	25.834us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	43.923us	20	20	100.00
		csrng_csr_aliasing	11.000s	822.186us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	45.600us	200	200	100.00
V2	alerts	csrng_alert	10.000s	77.548us	500	500	100.00
V2	err	csrng_err	14.000s	18.899us	485	500	97.00
V2	cmds	csrng_cmds	10.517m	66.894ms	50	50	100.00
V2	life cycle	csrng_cmds	10.517m	66.894ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.567m	67.148ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	42.991us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	14.613us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	953.409us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	953.409us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	228.041us	5	5	100.00
		csrng_csr_rw	8.000s	43.923us	20	20	100.00
		csrng_csr_aliasing	11.000s	822.186us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	129.255us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	228.041us	5	5	100.00
		csrng_csr_rw	8.000s	43.923us	20	20	100.00
		csrng_csr_aliasing	11.000s	822.186us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	129.255us	20	20	100.00
V2		TOTAL			1423	1440	98.82
V2S	tl_intg_err	csrng_sec_cm	12.000s	1.031ms	5	5	100.00
		csrng_tl_intg_err	15.000s	1.497ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	29.227us	50	50	100.00
		csrng_csr_rw	8.000s	43.923us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	77.548us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.567m	67.148ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	77.548us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.567m	67.148ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	77.548us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	1.497ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
		csrng_sec_cm	12.000s	1.031ms	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	45.600us	200	200	100.00
		csrng_err	14.000s	18.899us	485	500	97.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.852h	372.408ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1637	1670	98.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.70	93.20	84.21	95.34	86.30	92.29	98.18	97.50	94.52

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 11 failures:
- Test csrng_stress_all_with_rand_reset has 11 failures.
  - 0.csrng_stress_all_with_rand_reset.40174073724055369816689886892941421595205960748482442422830278892214500808985
    Line 806, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 347548281356 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 347548281356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.37694706800435218504032830422377571907584772080755468508499071264816473338567
    Line 543, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 235237556582 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 235237556582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

32.csrng_err.35267947423632934602702877361912510217413186210381091059945758123298644963328
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 29603728 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  29603728 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  29603728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.csrng_err.55050312163620497642761063878434796218457031946470795361385286096045004189686
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/53.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1594891 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1594891 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1594891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 2.csrng_stress_all_with_rand_reset.33579460566896249788487547186810433224697485443744133281768707699312551493495
    Line 449, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 51038333114 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 51038333114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.csrng_stress_all_with_rand_reset.109966081877819804324927580869704272844576500844617676549359199558827932988885
    Line 674, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 288068083597 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 288068083597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

38.csrng_err.28067829311522748761256992911096141627850379137383515204874251584240682571034
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3877330 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3877330 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3877330 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3877330 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3877330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

49.csrng_err.60066167974647033704498244970070619892632106921635579656714564987283015493085
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/49.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3089405 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3089405 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3089405 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3089405 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3089405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 8.csrng_stress_all.27926832849055279517257343059298023585070366360434978063630524493771286297083
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 21579193036 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 21579193036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.csrng_stress_all.27476802851321034010170024910929597201358743789460837070453111154201925340683
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  24551976 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  24551976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

141.csrng_err.78341689760177875492371289023137177541051504486341908748552709438656469401011
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/141.csrng_err/latest/run.log

  UVM_ERROR @   5919987 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5919987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

255.csrng_err.30265050408917436039960517320899890778094984803782390227498610407376917077815
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/255.csrng_err/latest/run.log

  UVM_ERROR @  11070845 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11070845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 36.csrng_stress_all_with_rand_reset.32923079597256934212184774489459225817401350666026914642005937409818925515869
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0d29e25f-cfcf-454d-b415-cd2485f2c5bc
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

281.csrng_err.115136694832433596338245466940491148435853529839467948269096674260409881671568
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/281.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  281.csrng_err.414922640
  
  coverage files:
    model(design data) :  /workspace/coverage/default/281.csrng_err.414922640/icc_045766fd_29c39fee.ucm
    data               :  /workspace/coverage/default/281.csrng_err.414922640/icc_045766fd_29c39fee.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jan 07, 2024 at 13:51:32 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1