CSRNG Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	150.624us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	18.955us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	59.182us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	23.000s	1.190ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	51.639us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	71.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	59.182us	20	20	100.00
		csrng_csr_aliasing	5.000s	51.639us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	291.473us	200	200	100.00
V2	alerts	csrng_alert	8.000s	463.856us	500	500	100.00
V2	err	csrng_err	9.000s	35.920us	487	500	97.40
V2	cmds	csrng_cmds	7.800m	46.293ms	50	50	100.00
V2	life cycle	csrng_cmds	7.800m	46.293ms	50	50	100.00
V2	stress_all	csrng_stress_all	37.933m	132.639ms	50	50	100.00
V2	intr_test	csrng_intr_test	5.000s	224.759us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	45.949us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	143.792us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	143.792us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	18.955us	5	5	100.00
		csrng_csr_rw	5.000s	59.182us	20	20	100.00
		csrng_csr_aliasing	5.000s	51.639us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	230.230us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	18.955us	5	5	100.00
		csrng_csr_rw	5.000s	59.182us	20	20	100.00
		csrng_csr_aliasing	5.000s	51.639us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	230.230us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	6.000s	221.596us	5	5	100.00
		csrng_tl_intg_err	10.000s	366.394us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	38.263us	50	50	100.00
		csrng_csr_rw	5.000s	59.182us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	463.856us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	37.933m	132.639ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	463.856us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	37.933m	132.639ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	463.856us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	366.394us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
		csrng_sec_cm	6.000s	221.596us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	291.473us	200	200	100.00
		csrng_err	9.000s	35.920us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	55.567m	195.671ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1607	1670	96.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.63	93.16	84.10	95.35	85.99	91.94	100.00	97.33	94.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test csrng_stress_all_with_rand_reset has 26 failures.
  - 0.csrng_stress_all_with_rand_reset.60703093757593016687584279393013288147905722478116037046163399410505641742206
    Line 338, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9878605438 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9878605438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.24107960859634519551792906002880645985963055861999805513883765289606690684600
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8835024526 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8835024526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test csrng_stress_all_with_rand_reset has 24 failures.
  - 1.csrng_stress_all_with_rand_reset.23857369598865484036386273267240695415111019515007682969659548249463256841702
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6085422727 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6085422727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.46492058290841355398395213868157788718837206273275495669377275064294095597640
    Line 279, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 310071857 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 310071857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 8 failures:

Test csrng_err has 8 failures.

91.csrng_err.69426232724579424630097135685080798995369597576639365094885301407417782822138
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/91.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 39568288 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 39568288 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 39568288 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  39568288 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  39568288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

135.csrng_err.100673938760402392556073937841410833003617554128294520140895566999447273706448
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/135.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2377302 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2377302 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2377302 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2377302 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2377302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed

has 4 failures:

Test csrng_err has 4 failures.

262.csrng_err.34774139043496065730599801725164933283383909268927610967667149237875390792890
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/262.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7458543 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7458543 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7458543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

277.csrng_err.13023663101642003982897343910774822736432900221366657178214347411325218631348
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/277.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3683456 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3683456 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3683456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 385.csrng_err.76440505136032484674632063143250937226244662101991372493480862839906153723088
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/385.csrng_err/latest/run.log
```
  UVM_ERROR @   5601925 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5601925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```