CSRNG Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	133.575us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	15.511us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	18.359us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	1.375ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	67.599us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	28.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	18.359us	20	20	100.00
		csrng_csr_aliasing	5.000s	67.599us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	31.919us	200	200	100.00
V2	alerts	csrng_alert	16.000s	216.101us	500	500	100.00
V2	err	csrng_err	14.000s	28.484us	491	500	98.20
V2	cmds	csrng_cmds	8.383m	45.531ms	50	50	100.00
V2	life cycle	csrng_cmds	8.383m	45.531ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.183m	56.453ms	49	50	98.00
V2	intr_test	csrng_intr_test	14.000s	45.450us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	54.273us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	295.780us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	295.780us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	15.511us	5	5	100.00
		csrng_csr_rw	8.000s	18.359us	20	20	100.00
		csrng_csr_aliasing	5.000s	67.599us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	28.663us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	15.511us	5	5	100.00
		csrng_csr_rw	8.000s	18.359us	20	20	100.00
		csrng_csr_aliasing	5.000s	67.599us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	28.663us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	9.000s	56.623us	5	5	100.00
		csrng_tl_intg_err	12.000s	676.759us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	42.949us	50	50	100.00
		csrng_csr_rw	8.000s	18.359us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.000s	216.101us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.183m	56.453ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.000s	216.101us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.183m	56.453ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.000s	216.101us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	676.759us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
		csrng_sec_cm	9.000s	56.623us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	31.919us	200	200	100.00
		csrng_err	14.000s	28.484us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.162h	169.176ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1610	1670	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.72	93.22	84.25	95.36	86.34	92.00	100.00	97.50	94.96

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 0.csrng_stress_all_with_rand_reset.107531049259749348549204414495966695175550593714165543343720898862102455369792
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121536902 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 121536902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.43739331674465662588890774469104222016181719394754718798294981834472306993885
    Line 280, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9984114858 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9984114858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 3.csrng_stress_all_with_rand_reset.107386884606348347809443673866379841642752246455880181134548608459111832679214
    Line 424, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9881082170 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9881082170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.95281826851164610054507847457052226210191388661766308505774116524665474280479
    Line 348, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16033209692 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16033209692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

101.csrng_err.112313027960211730766232697176727541435822875101024165106575395177682623327497
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2120705 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2120705 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2120705 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2120705 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2120705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

328.csrng_err.49141179301744723348754481867589074266744712709299474507557012828967244650874
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/328.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 13111692 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 13111692 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 13111692 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  13111692 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  13111692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

41.csrng_err.34549368163264815234297672976674446918031678609924967345905428757215138832339
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3039395 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3039395 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3039395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

350.csrng_err.88494268952808904651685329558381048390942052049906985345340490738761149799939
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/350.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4502417 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4502417 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4502417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 33.csrng_stress_all.3250311238554771813484736638378355875204971713124550534145267759333139167385
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6193866973 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6193866973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

94.csrng_err.107074173383150333563108347161354488850203998327644343753805111998949567029172
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/94.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  94.csrng_err.3443318708
  
  coverage files:
    model(design data) :  /workspace/coverage/default/94.csrng_err.3443318708/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/94.csrng_err.3443318708/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 07, 2024 at 12:50:12 PST  (total: 00:00:05)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 97.csrng_err.105871365598763807150326038577531351964833471714723090775626420943133468184641
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/97.csrng_err/latest/run.log
```
  UVM_ERROR @   5771552 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5771552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```