CSRNG Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	362.746us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	179.944us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	176.934us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	873.696us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	207.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	103.817us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	176.934us	20	20	100.00
		csrng_csr_aliasing	5.000s	207.157us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	5.000s	51.790us	200	200	100.00
V2	alerts	csrng_alert	9.000s	50.335us	500	500	100.00
V2	err	csrng_err	9.000s	22.811us	491	500	98.20
V2	cmds	csrng_cmds	7.283m	37.474ms	50	50	100.00
V2	life cycle	csrng_cmds	7.283m	37.474ms	50	50	100.00
V2	stress_all	csrng_stress_all	23.500m	36.180ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	56.979us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	44.918us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	26.000s	1.997ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	26.000s	1.997ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	179.944us	5	5	100.00
		csrng_csr_rw	4.000s	176.934us	20	20	100.00
		csrng_csr_aliasing	5.000s	207.157us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	187.660us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	179.944us	5	5	100.00
		csrng_csr_rw	4.000s	176.934us	20	20	100.00
		csrng_csr_aliasing	5.000s	207.157us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	187.660us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	7.000s	489.973us	5	5	100.00
		csrng_tl_intg_err	12.000s	864.146us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	92.135us	50	50	100.00
		csrng_csr_rw	4.000s	176.934us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	50.335us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.500m	36.180ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	50.335us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.500m	36.180ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	50.335us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	864.146us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
		csrng_sec_cm	7.000s	489.973us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	51.790us	200	200	100.00
		csrng_err	9.000s	22.811us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	37.217m	196.341ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1610	1670	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.71	93.22	84.25	95.36	86.34	92.00	100.00	97.50	94.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test csrng_stress_all_with_rand_reset has 32 failures.
  - 0.csrng_stress_all_with_rand_reset.94458156160275779743484741995359980678170105011762501324988911646526459804177
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 920656166 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 920656166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.87107236778277858521148604406124430733061162263773702358875556530132994397973
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19371739862 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19371739862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test csrng_stress_all_with_rand_reset has 18 failures.
  - 5.csrng_stress_all_with_rand_reset.30190073239755042975963839133075037755650350715250054684645597399568037191080
    Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6225221070 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6225221070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.76041407160573651544266561534992697997143793406774338320635627794990224886111
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 302372180 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 302372180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

19.csrng_err.81925290676464827682438290604887130977824524514631683487640665574461939407243
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2416262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2416262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2416262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2416262 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2416262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

96.csrng_err.9555254567132530496745167923794812187670450885984127414221895955743603596416
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/96.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5958596 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5958596 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5958596 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5958596 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5958596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

44.csrng_err.9263409307520291690119049625116705695088850410551354294386714932314693376689
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  44.csrng_err.2319915697
  
  coverage files:
    model(design data) :  /workspace/coverage/default/44.csrng_err.2319915697/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/44.csrng_err.2319915697/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 05, 2024 at 14:53:06 PST  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

222.csrng_err.25610779580917564623530548136594493581461317044193931751786733162894681468746
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/222.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  222.csrng_err.526675786
  
  coverage files:
    model(design data) :  /workspace/coverage/default/222.csrng_err.526675786/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/222.csrng_err.526675786/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 05, 2024 at 14:54:56 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

121.csrng_err.30267302259614067647103065802096315707034151844390222408257527189103923323068
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/121.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4016586 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4016586 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4016586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

158.csrng_err.24765968304632751309378477076081734800836631896946434730184303146879428526979
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/158.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4353832 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4353832 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4353832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.71213373667933305080882158505286481953408157684786591727461238581003604169145
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  51430806 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  51430806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```