CSRNG Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	378.689us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	44.582us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	37.212us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	15.000s	706.905us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	136.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	18.066us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	37.212us	20	20	100.00
		csrng_csr_aliasing	6.000s	136.178us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	156.251us	200	200	100.00
V2	alerts	csrng_alert	20.000s	421.470us	500	500	100.00
V2	err	csrng_err	15.000s	69.622us	489	500	97.80
V2	cmds	csrng_cmds	6.033m	25.298ms	50	50	100.00
V2	life cycle	csrng_cmds	6.033m	25.298ms	50	50	100.00
V2	stress_all	csrng_stress_all	26.383m	79.572ms	45	50	90.00
V2	intr_test	csrng_intr_test	4.000s	115.484us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	152.686us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	144.856us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	144.856us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	44.582us	5	5	100.00
		csrng_csr_rw	8.000s	37.212us	20	20	100.00
		csrng_csr_aliasing	6.000s	136.178us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	136.217us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	44.582us	5	5	100.00
		csrng_csr_rw	8.000s	37.212us	20	20	100.00
		csrng_csr_aliasing	6.000s	136.178us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	136.217us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	8.000s	529.295us	5	5	100.00
		csrng_tl_intg_err	17.000s	319.077us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	152.050us	50	50	100.00
		csrng_csr_rw	8.000s	37.212us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	20.000s	421.470us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	26.383m	79.572ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	20.000s	421.470us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	26.383m	79.572ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	20.000s	421.470us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	319.077us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
		csrng_sec_cm	8.000s	529.295us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	156.251us	200	200	100.00
		csrng_err	15.000s	69.622us	489	500	97.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.560h	616.202ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1604	1670	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.69	93.20	84.21	95.34	86.30	92.00	100.00	97.50	94.85

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:816) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 1.csrng_stress_all_with_rand_reset.52384595839867970742421623462462141844919646810848198171541618658227600786113
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3156542775 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3156542775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.70695872031760777095029193100521271742450480432515313993729195241502971530217
    Line 280, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2855675410 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2855675410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:816) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 0.csrng_stress_all_with_rand_reset.50276997638155440884571482635501230504701830337659935750970236747667525637947
    Line 279, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2660535130 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2660535130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.76119323982155268982825794247722269019124784011609112125479234699438829734157
    Line 348, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6336091574 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6336091574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

169.csrng_err.39266313512629198642020453996473434058343226140044674571676758130847821292114
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/169.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 21766356 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  21766356 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  21766356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

214.csrng_err.107393135487498416563531955819007908923816691496986827771973551243435013721083
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/214.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7415037 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7415037 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7415037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 0.csrng_stress_all.51311699365834165040693225332720609703304252938004510686536639714179183952297
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8474749815 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8474749815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all.60879115989943791550395919338952121530604183433197905202114530722243002160506
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5409448354 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5409448354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

40.csrng_err.59332664603750215375437671921550550968477567890241301542366695893901313125071
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6906449 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6906449 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6906449 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   6906449 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   6906449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

223.csrng_err.80878553004495290290112238172422952491965333281158365805656897627135061186859
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/223.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3250955 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3250955 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3250955 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3250955 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3250955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 34.csrng_stress_all.7504895441434568417880652206472512263152794312280621084815787447938175471659
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 281411243 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 281411243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

149.csrng_err.26430201831843603159336240161587447665120884164308503347367562020892209905095
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/149.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  149.csrng_err.1187052999
  
  coverage files:
    model(design data) :  /workspace/coverage/default/149.csrng_err.1187052999/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/149.csrng_err.1187052999/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 03, 2024 at 12:26:33 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1