CSRNG Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	14.384us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	193.665us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	61.404us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	899.429us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	47.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	539.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	61.404us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.635us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	28.813us	200	200	100.00
V2	alerts	csrng_alert	15.000s	178.402us	500	500	100.00
V2	err	csrng_err	18.000s	33.730us	490	500	98.00
V2	cmds	csrng_cmds	7.150m	46.247ms	50	50	100.00
V2	life cycle	csrng_cmds	7.150m	46.247ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.917m	150.382ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	41.484us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	23.416us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	887.643us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	887.643us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	193.665us	5	5	100.00
		csrng_csr_rw	5.000s	61.404us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.635us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	52.915us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	193.665us	5	5	100.00
		csrng_csr_rw	5.000s	61.404us	20	20	100.00
		csrng_csr_aliasing	5.000s	47.635us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	52.915us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	12.000s	330.219us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.158ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	29.122us	50	50	100.00
		csrng_csr_rw	5.000s	61.404us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	178.402us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.917m	150.382ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	178.402us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.917m	150.382ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	178.402us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.158ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
		csrng_sec_cm	12.000s	330.219us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	28.813us	200	200	100.00
		csrng_err	18.000s	33.730us	490	500	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.289h	50.181ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1609	1670	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.65	93.18	84.17	95.30	86.30	91.88	100.00	97.17	94.85

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 0.csrng_stress_all_with_rand_reset.11259632216693337738157021537151829185586871713306240868325833228555502905168
    Line 362, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13420643863 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13420643863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.57477631621128802434546382058733300866926933686288877740458308961189506852021
    Line 500, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41763438918 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41763438918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 3.csrng_stress_all_with_rand_reset.57159250341034221286875721263998262159790852277359638607666392265439497674609
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 997042803 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 997042803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.55408026307750447107763739186297314164723978082968053821876994701498259422177
    Line 480, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49558700251 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49558700251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

49.csrng_err.46779734971440959431229421403883476394890635422825456986368314394025679970045
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/49.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5337098 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5337098 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5337098 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5337098 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5337098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

55.csrng_err.56615599477313944875103916597560549828892464535718847346698516396427617935043
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/55.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2297543 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2297543 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2297543 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2297543 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2297543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

5.csrng_err.55195787629451249586797417285745154397140338407822436806307008611168185263995
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4135924 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   4135924 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4135924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

383.csrng_err.94834231287919135589847989544665317875337235005610603837447642163129467510647
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/383.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 8067266 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8067266 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8067266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 0.csrng_stress_all.87273687840571278209840476868782471046556184311128188637224481348883538323970
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2637232116 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2637232116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 397.csrng_err.76498209899496188270095662500206309715481852159746803035318604184495608898383
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/397.csrng_err/latest/run.log
```
  UVM_ERROR @   6064557 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   6064557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```