CSRNG Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	23.928us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	16.911us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	274.010us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	333.069us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	43.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	230.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	274.010us	20	20	100.00
		csrng_csr_aliasing	5.000s	43.635us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	124.734us	200	200	100.00
V2	alerts	csrng_alert	14.000s	26.522us	500	500	100.00
V2	err	csrng_err	9.000s	48.840us	481	500	96.20
V2	cmds	csrng_cmds	7.767m	39.407ms	49	50	98.00
V2	life cycle	csrng_cmds	7.767m	39.407ms	49	50	98.00
V2	stress_all	csrng_stress_all	17.100m	22.014ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	137.688us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	14.280us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	1.157ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	1.157ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	16.911us	5	5	100.00
		csrng_csr_rw	5.000s	274.010us	20	20	100.00
		csrng_csr_aliasing	5.000s	43.635us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	142.530us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	16.911us	5	5	100.00
		csrng_csr_rw	5.000s	274.010us	20	20	100.00
		csrng_csr_aliasing	5.000s	43.635us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	142.530us	20	20	100.00
V2		TOTAL			1418	1440	98.47
V2S	tl_intg_err	csrng_sec_cm	6.000s	88.573us	5	5	100.00
		csrng_tl_intg_err	12.000s	611.569us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	35.130us	50	50	100.00
		csrng_csr_rw	5.000s	274.010us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	14.000s	26.522us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	17.100m	22.014ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	14.000s	26.522us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	17.100m	22.014ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	14.000s	26.522us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	611.569us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
		csrng_sec_cm	6.000s	88.573us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	124.734us	200	200	100.00
		csrng_err	9.000s	48.840us	481	500	96.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.651h	192.989ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1598	1670	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.65	93.16	84.10	95.39	85.99	91.94	100.00	97.33	94.96

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 0.csrng_stress_all_with_rand_reset.23283922496004018238041789525103991296867366492921695766422610335838177984292
    Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6595575278 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6595575278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.52231249887745907386237407513689052776287885938846846699929204738942522811391
    Line 350, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87597895316 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87597895316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:828) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 1.csrng_stress_all_with_rand_reset.103954873478247199574862343565870956735065558959023205846002589597681318606498
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 220898227 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 220898227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.81515232041965443436709119831249637676252724799259201367611788813987272225994
    Line 279, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 911917415 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 911917415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

76.csrng_err.38144559142112261102278354390163860108093148794355042652807311174015479463201
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/76.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5506567 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5506567 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5506567 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5506567 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5506567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

80.csrng_err.71098165398449979192268568770583063059192928044821503901559394064023437722963
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/80.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2221778 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2221778 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2221778 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2221778 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2221778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

19.csrng_err.60740406885941374921914180567855131939137548839495129648185696579544017487872
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2180403 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2180403 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2180403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

64.csrng_err.56494735100213185644998735011938588348906360297385654749891959513931817605691
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/64.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 10581238 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  10581238 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10581238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

148.csrng_err.46681234687598899651203510385641188022079616948786973065927459564003700964092
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/148.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  148.csrng_err.2934110972
  
  coverage files:
    model(design data) :  /workspace/coverage/default/148.csrng_err.2934110972/icc_265e29af_62cdf96e.ucm
    data               :  /workspace/coverage/default/148.csrng_err.2934110972/icc_265e29af_62cdf96e.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 19, 2024 at 15:00:20 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

200.csrng_err.104624313516034485436095192999388972522162633947047909123499348489938287688493
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/200.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  200.csrng_err.3879435053
  
  coverage files:
    model(design data) :  /workspace/coverage/default/200.csrng_err.3879435053/icc_265e29af_62cdf96e.ucm
    data               :  /workspace/coverage/default/200.csrng_err.3879435053/icc_265e29af_62cdf96e.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 19, 2024 at 15:00:54 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 25.csrng_stress_all.78352662037174374095255312481361123710721373145623973272918279577890846734841
    Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5242036973 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5242036973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.csrng_stress_all.43302418126655865967607734238882596408997017132131373838230420215318278532205
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 17347504349 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 17347504349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_scoreboard.sv:309) [scoreboard] Check failed (read_data >> *) & *'b* == cfg.compliance[SW_APP] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 12.csrng_cmds.6733615432921072358027335479723272829210556399419120991527334355399682611198
    Line 327, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 1312888810 ps: (csrng_scoreboard.sv:309) [uvm_test_top.env.scoreboard] Check failed (read_data >> 1) & 1'b1 == cfg.compliance[SW_APP] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1312888810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```