CSRNG Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	166.833us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	19.287us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	56.195us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	590.266us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	227.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	40.136us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	56.195us	20	20	100.00
		csrng_csr_aliasing	6.000s	227.251us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	31.467us	200	200	100.00
V2	alerts	csrng_alert	22.000s	100.843us	500	500	100.00
V2	err	csrng_err	20.000s	40.326us	486	500	97.20
V2	cmds	csrng_cmds	6.683m	39.352ms	50	50	100.00
V2	life cycle	csrng_cmds	6.683m	39.352ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.467m	206.636ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	160.961us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	40.872us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	458.352us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	458.352us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	19.287us	5	5	100.00
		csrng_csr_rw	8.000s	56.195us	20	20	100.00
		csrng_csr_aliasing	6.000s	227.251us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	282.650us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	19.287us	5	5	100.00
		csrng_csr_rw	8.000s	56.195us	20	20	100.00
		csrng_csr_aliasing	6.000s	227.251us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	282.650us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	7.000s	410.796us	5	5	100.00
		csrng_tl_intg_err	13.000s	636.469us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	36.495us	50	50	100.00
		csrng_csr_rw	8.000s	56.195us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	22.000s	100.843us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.467m	206.636ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	22.000s	100.843us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.467m	206.636ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	22.000s	100.843us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	636.469us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
		csrng_sec_cm	7.000s	410.796us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	31.467us	200	200	100.00
		csrng_err	20.000s	40.326us	486	500	97.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.378h	103.315ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1605	1670	96.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.62	93.14	84.06	95.35	85.95	92.00	100.00	97.50	94.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test csrng_stress_all_with_rand_reset has 37 failures.
  - 0.csrng_stress_all_with_rand_reset.105585842143570451220760965725502349919148503650590431303436809703037474995795
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10303680096 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10303680096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.67449194842356465088563758139951793516329936954161510969976310538518767499401
    Line 391, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19092287062 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19092287062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 4.csrng_stress_all_with_rand_reset.55939626186472343320674144037103318297239228633086235362749359289643944281593
    Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 425560599 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 425560599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.39423580124305400362178954334935836379304087342256632566797950855787355058101
    Line 281, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1955566114 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1955566114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

32.csrng_err.50383591936934639203784233473491215620697815365017518605195203261415375518510
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7712310 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7712310 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7712310 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   7712310 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   7712310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

34.csrng_err.102978833821645317969869175752025238842754146611929661526164376749992417957994
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3389043 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3389043 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3389043 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3389043 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3389043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

117.csrng_err.30100723817756897981101048176941524125930312374843036552183767699853758967925
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/117.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1749775 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1749775 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1749775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

159.csrng_err.70720329593383289752593539149308783001932472869701297457833335894423972475328
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/159.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6410866 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6410866 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6410866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

261.csrng_err.61394755425280640886071601424837631238931673064723033225848827299813324519416
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/261.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  261.csrng_err.651458552
  
  coverage files:
    model(design data) :  /workspace/coverage/default/261.csrng_err.651458552/icc_265e29af_62cdf96e.ucm
    data               :  /workspace/coverage/default/261.csrng_err.651458552/icc_265e29af_62cdf96e.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 21, 2024 at 12:31:42 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

420.csrng_err.70409271736331582148320106370473895188621381709104720517636683819852631299436
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/420.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  420.csrng_err.872600940
  
  coverage files:
    model(design data) :  /workspace/coverage/default/420.csrng_err.872600940/icc_265e29af_62cdf96e.ucm
    data               :  /workspace/coverage/default/420.csrng_err.872600940/icc_265e29af_62cdf96e.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 21, 2024 at 12:32:33 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 7.csrng_stress_all.72978209254854547690095449901708213108704964773634516934299346710865874952590
    Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5806841896 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5806841896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```