70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 5.000s | 65.579us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 37.496us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 9.000s | 26.353us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 19.000s | 922.186us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 10.000s | 77.499us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 9.000s | 84.330us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 9.000s | 26.353us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 10.000s | 77.499us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 9.000s | 617.350us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 |
| V2 | cmds | csrng_cmds | 13.283m | 54.572ms | 49 | 50 | 98.00 |
| V2 | life cycle | csrng_cmds | 13.283m | 54.572ms | 49 | 50 | 98.00 |
| V2 | stress_all | csrng_stress_all | 23.983m | 60.094ms | 45 | 50 | 90.00 |
| V2 | intr_test | csrng_intr_test | 9.000s | 14.979us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 5.000s | 36.205us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 17.000s | 1.212ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 17.000s | 1.212ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 37.496us | 5 | 5 | 100.00 |
| csrng_csr_rw | 9.000s | 26.353us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 10.000s | 77.499us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 10.000s | 126.920us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 37.496us | 5 | 5 | 100.00 |
| csrng_csr_rw | 9.000s | 26.353us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 10.000s | 77.499us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 10.000s | 126.920us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1418 | 1440 | 98.47 | |||
| V2S | tl_intg_err | csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 1.033m | 1.234ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 4.000s | 35.546us | 50 | 50 | 100.00 |
| csrng_csr_rw | 9.000s | 26.353us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 9.000s | 617.350us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 23.983m | 60.094ms | 45 | 50 | 90.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 9.000s | 617.350us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 23.983m | 60.094ms | 45 | 50 | 90.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 9.000s | 617.350us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 1.033m | 1.234ms | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| csrng_sec_cm | 8.000s | 185.974us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 6.000s | 331.330us | 200 | 200 | 100.00 |
| csrng_err | 4.000s | 19.506us | 484 | 500 | 96.80 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 2.074h | 561.923ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1598 | 1670 | 95.69 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 6 | 66.67 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.64 | 93.16 | 84.10 | 95.38 | 85.95 | 92.00 | 100.00 | 97.50 | 94.52 |
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
2.csrng_stress_all_with_rand_reset.36015882711755226869949701125179957423190955734948324188329026407722426450124
Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2853928938 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2853928938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.csrng_stress_all_with_rand_reset.102326529488563922261754923507821364786579223692208846313792001332239414746995
Line 369, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14352591245 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14352591245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.csrng_stress_all_with_rand_reset.3367977682878006152183942229789315369459151817804622199615164681374677488234
Line 281, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3863514788 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3863514788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_stress_all_with_rand_reset.75652643993308467408796706040911033069054185924553098404171052537025117698573
Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3882124273 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3882124273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 8 failures:
35.csrng_err.95180973155389140038515826663903348868461752267983754013855752476546611285445
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2083920 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2083920 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2083920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
52.csrng_err.30432275755058515290490392044977289412325474633794871046455092055319021350023
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/52.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1821909 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 1821909 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1821909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:
121.csrng_err.25300123977572569177365975682270692038448984795206910703817053494498340315402
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/121.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7227821 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7227821 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7227821 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 7227821 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 7227821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
295.csrng_err.47861926311408779321095703451310656596927967823644217303387288255336265619792
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/295.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1997519 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1997519 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1997519 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1997519 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1997519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
20.csrng_stress_all.65291529768084627965720849576845509208261952814537193268073072630010645299411
Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
UVM_ERROR @ 6997017693 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 6997017693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.csrng_stress_all.22802277980472520302754081296305586606944860320417371333808706706052976966081
Line 347, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
UVM_ERROR @ 65808212910 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 65808212910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
10.csrng_stress_all.38432933694456869373728096911174038782241616193229808488992113453814921128840
Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
UVM_ERROR @ 57165488754 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 57165488754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.csrng_stress_all.110057950035705120416310040799426747997439470142376844890843223427624581415840
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log
UVM_ERROR @ 460940595 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 460940595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
227.csrng_err.41201978721941830004121517544719560543398970411971118450301987871494162955282
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/227.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 227.csrng_err.3911531538
coverage files:
model(design data) : /workspace/coverage/default/227.csrng_err.3911531538/icc_0b7b4e9f_62cdf96e.ucm
data : /workspace/coverage/default/227.csrng_err.3911531538/icc_0b7b4e9f_62cdf96e.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Mar 24, 2024 at 15:04:46 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1
335.csrng_err.55134464433241307009052654793499141188950558453771403604138548371352245664877
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/335.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 335.csrng_err.3489823853
coverage files:
model(design data) : /workspace/coverage/default/335.csrng_err.3489823853/icc_0b7b4e9f_62cdf96e.ucm
data : /workspace/coverage/default/335.csrng_err.3489823853/icc_0b7b4e9f_62cdf96e.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Mar 24, 2024 at 15:05:38 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1
UVM_FATAL (csrng_scoreboard.sv:326) [scoreboard] Check failed cs_item[SW_APP].genbits_q[i] == prd_genbits_q[SW_APP][i] (* [*] vs * [*]) has 1 failures:
13.csrng_cmds.106516021975510568950592311004693620211062889492468934207198639689999466399234
Line 387, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_cmds/latest/run.log
UVM_FATAL @ 9864404510 ps: (csrng_scoreboard.sv:326) [uvm_test_top.env.scoreboard] Check failed cs_item[SW_APP].genbits_q[i] == prd_genbits_q[SW_APP][i] (113451752590438054815376585099657668862 [0x555a0343f55d182f8b03d79027e8e8fe] vs 270631593058003109273002944114664657463 [0xcb99bfb7b2c0b95d6f6a01371b87d237])
UVM_INFO @ 9864404510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
409.csrng_err.10387556577286432385526420209006403444765050826236163788475799571852768563897
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/409.csrng_err/latest/run.log
UVM_ERROR @ 3132146 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 3132146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---