CSRNG Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	218.719us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	52.891us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	71.081us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	475.474us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	106.626us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	51.237us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	71.081us	20	20	100.00
		csrng_csr_aliasing	5.000s	106.626us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	29.906us	200	200	100.00
V2	alerts	csrng_alert	15.000s	92.700us	500	500	100.00
V2	err	csrng_err	19.000s	36.554us	491	500	98.20
V2	cmds	csrng_cmds	7.333m	12.344ms	50	50	100.00
V2	life cycle	csrng_cmds	7.333m	12.344ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.350m	71.173ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	56.586us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	40.108us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	537.344us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	537.344us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	52.891us	5	5	100.00
		csrng_csr_rw	4.000s	71.081us	20	20	100.00
		csrng_csr_aliasing	5.000s	106.626us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	334.804us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	52.891us	5	5	100.00
		csrng_csr_rw	4.000s	71.081us	20	20	100.00
		csrng_csr_aliasing	5.000s	106.626us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	334.804us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	34.000s	672.909us	5	5	100.00
		csrng_tl_intg_err	13.000s	217.597us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	79.033us	50	50	100.00
		csrng_csr_rw	4.000s	71.081us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	92.700us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.350m	71.173ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	92.700us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.350m	71.173ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	92.700us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	217.597us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
		csrng_sec_cm	34.000s	672.909us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	29.906us	200	200	100.00
		csrng_err	19.000s	36.554us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.428h	158.239ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1609	1670	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.65	93.16	84.10	95.37	85.99	92.00	100.00	97.50	95.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test csrng_stress_all_with_rand_reset has 30 failures.
  - 0.csrng_stress_all_with_rand_reset.96827164682587042047514461268806804685628053245555198049559560796459995874964
    Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36332684652 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36332684652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.44620452764107405620996951657407128264608426101184118701379084034766583409722
    Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17858492332 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17858492332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test csrng_stress_all_with_rand_reset has 20 failures.
  - 1.csrng_stress_all_with_rand_reset.98441548065826221766946752943269446095923733430253784242555525971022372145736
    Line 281, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4015575707 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4015575707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.64616749886190784211057274207943013933506731590207170152529926818720801572198
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70160466834 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 70160466834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

77.csrng_err.13326647019082196713447809478228014763354948911804262192365652726841925268104
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/77.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3981270 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3981270 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3981270 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3981270 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3981270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

149.csrng_err.41057349497116594211575290473436373165711332677951413275632954312410572246914
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/149.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2364929 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2364929 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2364929 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2364929 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2364929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

139.csrng_err.29485519211783204538028459991146356566012767885631713297067312517074639762922
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/139.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3152776 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3152776 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3152776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

302.csrng_err.1423376009998200672471233165288318087017504616391037151134201944367314450429
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/302.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1835900 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1835900 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1835900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 15.csrng_stress_all.64461450993861447081845953809322262430117482728063908461767269106948621099994
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  40751476 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  40751476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 21.csrng_stress_all.57664466459578611484044187194207433303979383259410440036329281608878327593828
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 15829995853 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 15829995853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```