CSRNG Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	57.852us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	89.123us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	205.210us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	2.066ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	213.550us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	386.175us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	205.210us	20	20	100.00
		csrng_csr_aliasing	6.000s	213.550us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	286.025us	200	200	100.00
V2	alerts	csrng_alert	9.000s	479.742us	500	500	100.00
V2	err	csrng_err	5.000s	20.847us	484	500	96.80
V2	cmds	csrng_cmds	12.833m	63.536ms	50	50	100.00
V2	life cycle	csrng_cmds	12.833m	63.536ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.067m	99.389ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	41.687us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	201.582us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	810.270us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	810.270us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	89.123us	5	5	100.00
		csrng_csr_rw	5.000s	205.210us	20	20	100.00
		csrng_csr_aliasing	6.000s	213.550us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	148.252us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	89.123us	5	5	100.00
		csrng_csr_rw	5.000s	205.210us	20	20	100.00
		csrng_csr_aliasing	6.000s	213.550us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	148.252us	20	20	100.00
V2		TOTAL			1421	1440	98.68
V2S	tl_intg_err	csrng_sec_cm	10.000s	975.523us	5	5	100.00
		csrng_tl_intg_err	10.000s	723.897us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	13.141us	50	50	100.00
		csrng_csr_rw	5.000s	205.210us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	479.742us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.067m	99.389ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	479.742us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.067m	99.389ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	479.742us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	723.897us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
		csrng_sec_cm	10.000s	975.523us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	286.025us	200	200	100.00
		csrng_err	5.000s	20.847us	484	500	96.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.188h	77.820ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1601	1670	95.87

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.61	93.14	84.06	95.33	85.99	92.00	100.00	97.50	94.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 1.csrng_stress_all_with_rand_reset.115374669038321018471808524890301708561997734943735780107019535426481933152831
    Line 404, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40792617975 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 40792617975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.18252554965791462757658524466824537801762381468338292876584195973892503406381
    Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3493787577 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3493787577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 0.csrng_stress_all_with_rand_reset.104644825004164798970109131857672726887271233852129708330029535380291038184130
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 988161002 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 988161002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.32436587416804366046504673860435429322071985802859478211138388892055188452032
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8233914211 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8233914211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

39.csrng_err.17268488722733979747866217934961486925811292444801941015665826397217781923094
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7432182 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7432182 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7432182 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   7432182 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   7432182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

45.csrng_err.16394801031046287688895983660253809871691188841851696323741246938805059345934
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3098624 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3098624 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3098624 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3098624 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3098624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

67.csrng_err.101188682843477328303338421819089247961671741319754374446145824582441013002766
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/67.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2588567 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2588567 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2588567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

142.csrng_err.4262984291098143753977530231322890615000501179032644181884749015400366277402
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/142.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1551986 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1551986 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1551986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 38.csrng_stress_all.57060103213610850713907829707207674753588792180776977476009799233991627993693
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3872828412 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3872828412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.csrng_stress_all.109375062661260578253253720507645951596921018173023335043067942790274906279954
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 158056810 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 158056810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 21.csrng_stress_all.22928414302152951475939756786763218308168324685445633751259592708416791302161
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 20177194406 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 20177194406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 391.csrng_err.29413918189639879385073671779154986975529356299359739972138344372541242307651
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/391.csrng_err/latest/run.log
```
  UVM_ERROR @  21520391 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  21520391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```