CSRNG Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 8.000s 17.216us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 4.000s 44.839us 5 5 100.00
V1 csr_rw csrng_csr_rw 4.000s 30.592us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 34.000s 3.342ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 5.000s 110.899us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 10.000s 26.612us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 4.000s 30.592us 20 20 100.00
csrng_csr_aliasing 5.000s 110.899us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 9.000s 26.605us 200 200 100.00
V2 alerts csrng_alert 9.000s 26.224us 500 500 100.00
V2 err csrng_err 9.000s 19.682us 488 500 97.60
V2 cmds csrng_cmds 9.700m 61.336ms 50 50 100.00
V2 life cycle csrng_cmds 9.700m 61.336ms 50 50 100.00
V2 stress_all csrng_stress_all 43.600m 227.402ms 48 50 96.00
V2 intr_test csrng_intr_test 13.000s 128.016us 50 50 100.00
V2 alert_test csrng_alert_test 9.000s 49.357us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 14.000s 635.315us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 14.000s 635.315us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 4.000s 44.839us 5 5 100.00
csrng_csr_rw 4.000s 30.592us 20 20 100.00
csrng_csr_aliasing 5.000s 110.899us 5 5 100.00
csrng_same_csr_outstanding 9.000s 78.624us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 4.000s 44.839us 5 5 100.00
csrng_csr_rw 4.000s 30.592us 20 20 100.00
csrng_csr_aliasing 5.000s 110.899us 5 5 100.00
csrng_same_csr_outstanding 9.000s 78.624us 20 20 100.00
V2 TOTAL 1426 1440 99.03
V2S tl_intg_err csrng_sec_cm 10.000s 152.822us 5 5 100.00
csrng_tl_intg_err 11.000s 876.902us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 5.000s 106.370us 50 50 100.00
csrng_csr_rw 4.000s 30.592us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 9.000s 26.224us 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 43.600m 227.402ms 48 50 96.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 9.000s 26.224us 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
V2S sec_cm_constants_lc_gated csrng_stress_all 43.600m 227.402ms 48 50 96.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 9.000s 26.224us 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 11.000s 876.902us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
csrng_sec_cm 10.000s 152.822us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 9.000s 26.605us 200 200 100.00
csrng_err 9.000s 19.682us 488 500 97.60
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 1.097h 163.541ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 1606 1670 96.17

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 7 77.78
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.67 93.19 84.19 95.40 85.99 92.00 98.18 97.50 94.74

Failure Buckets

Past Results