CSRNG Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	17.216us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	44.839us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	30.592us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	34.000s	3.342ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	110.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	26.612us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	30.592us	20	20	100.00
		csrng_csr_aliasing	5.000s	110.899us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	26.605us	200	200	100.00
V2	alerts	csrng_alert	9.000s	26.224us	500	500	100.00
V2	err	csrng_err	9.000s	19.682us	488	500	97.60
V2	cmds	csrng_cmds	9.700m	61.336ms	50	50	100.00
V2	life cycle	csrng_cmds	9.700m	61.336ms	50	50	100.00
V2	stress_all	csrng_stress_all	43.600m	227.402ms	48	50	96.00
V2	intr_test	csrng_intr_test	13.000s	128.016us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	49.357us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	635.315us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	635.315us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	44.839us	5	5	100.00
		csrng_csr_rw	4.000s	30.592us	20	20	100.00
		csrng_csr_aliasing	5.000s	110.899us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	78.624us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	44.839us	5	5	100.00
		csrng_csr_rw	4.000s	30.592us	20	20	100.00
		csrng_csr_aliasing	5.000s	110.899us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	78.624us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	10.000s	152.822us	5	5	100.00
		csrng_tl_intg_err	11.000s	876.902us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	106.370us	50	50	100.00
		csrng_csr_rw	4.000s	30.592us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	26.224us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	43.600m	227.402ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	26.224us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	43.600m	227.402ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	26.224us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	876.902us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
		csrng_sec_cm	10.000s	152.822us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	26.605us	200	200	100.00
		csrng_err	9.000s	19.682us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.097h	163.541ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1606	1670	96.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.67	93.19	84.19	95.40	85.99	92.00	98.18	97.50	94.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test csrng_stress_all_with_rand_reset has 32 failures.
  - 0.csrng_stress_all_with_rand_reset.74876756789442173962461090299271334141113818594113941685648569767118211047968
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5668643834 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5668643834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.46861709129736284320731408994709002212161022685825120797301974267886652969741
    Line 294, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5160110673 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5160110673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test csrng_stress_all_with_rand_reset has 18 failures.
  - 1.csrng_stress_all_with_rand_reset.107920925410038181096484235259383132452163558594249203475769353449353972143346
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39784491368 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39784491368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.60151448525729277495867990354859645611154377119611132854280227735426905781987
    Line 294, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11234943737 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11234943737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

133.csrng_err.89296103587625082768614000979860117656304054897533600000086919894575700815289
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/133.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 8318501 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8318501 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8318501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

352.csrng_err.109515855161381713823146481195662691847401295353511765616577991433814602802456
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/352.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 9325805 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   9325805 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   9325805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

182.csrng_err.12853025401044464449139631323823885042928644579433539246889096029538010152064
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/182.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 11631024 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 11631024 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 11631024 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  11631024 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  11631024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

209.csrng_err.84778776422086409205370598744056937472483974089175337123252748091237636341392
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/209.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 8878402 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 8878402 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 8878402 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   8878402 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   8878402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

3.csrng_err.2465242169709424202728097559578133348343150822741710159064713431850530326678
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_err/latest/run.log

  UVM_ERROR @  11038118 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11038118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

291.csrng_err.3267313421334816698828791602152684667550921923408288157116517559733886861055
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/291.csrng_err/latest/run.log

  UVM_ERROR @   3061625 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3061625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 12.csrng_stress_all.100610478133349506732097130390961620610849046456364992079896821087402450540525
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3507410726 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3507410726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.csrng_stress_all.83564720034466893073200412950118513556313977060111321921729609531716561797641
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3292496178 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3292496178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

104.csrng_err.54928880421554910653516850067509675394140840147243008558281366523321805885556
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  104.csrng_err.3953578100
  
  coverage files:
    model(design data) :  /workspace/coverage/default/104.csrng_err.3953578100/icc_0b7b4e9f_62cdf96e.ucm
    data               :  /workspace/coverage/default/104.csrng_err.3953578100/icc_0b7b4e9f_62cdf96e.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Mar 31, 2024 at 15:41:02 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1