CSRNG Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: `7773b039d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	22.560us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	44.055us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	11.331us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	11.000s	224.748us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	83.994us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	57.196us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	11.331us	20	20	100.00
		csrng_csr_aliasing	6.000s	83.994us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	38.020us	200	200	100.00
V2	alerts	csrng_alert	19.000s	31.336us	500	500	100.00
V2	err	csrng_err	14.000s	26.602us	488	500	97.60
V2	cmds	csrng_cmds	8.350m	22.896ms	50	50	100.00
V2	life cycle	csrng_cmds	8.350m	22.896ms	50	50	100.00
V2	stress_all	csrng_stress_all	35.083m	133.874ms	46	50	92.00
V2	intr_test	csrng_intr_test	13.000s	41.455us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	12.557us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	1.153ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	1.153ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	44.055us	5	5	100.00
		csrng_csr_rw	5.000s	11.331us	20	20	100.00
		csrng_csr_aliasing	6.000s	83.994us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	409.800us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	44.055us	5	5	100.00
		csrng_csr_rw	5.000s	11.331us	20	20	100.00
		csrng_csr_aliasing	6.000s	83.994us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	409.800us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	7.000s	546.193us	5	5	100.00
		csrng_tl_intg_err	16.000s	1.585ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	32.501us	50	50	100.00
		csrng_csr_rw	5.000s	11.331us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	19.000s	31.336us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	35.083m	133.874ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	19.000s	31.336us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	35.083m	133.874ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	19.000s	31.336us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	1.585ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
		csrng_sec_cm	7.000s	546.193us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	38.020us	200	200	100.00
		csrng_err	14.000s	26.602us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.834h	377.173ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1604	1670	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.64	93.16	84.10	95.37	85.99	92.00	100.00	97.50	94.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 0.csrng_stress_all_with_rand_reset.46957946396571411583041451307730454210157075231627273906406762823200959390306
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64868886443 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 64868886443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.109546813986811226070132200409413671516040950277813436630465967112131750397510
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3742378211 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3742378211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 5.csrng_stress_all_with_rand_reset.54029849787775947413180319606278469116091047656190696481060876482680670953707
    Line 591, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 93066458350 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 93066458350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.5319360171461946445942216341284483171246331898228080214162664120719363665358
    Line 380, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25401992675 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25401992675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 8 failures:

Test csrng_err has 8 failures.

6.csrng_err.34548376612146762019495051724018837131138828749625165780196491081238451898214
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2806750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2806750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2806750 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2806750 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2806750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

59.csrng_err.74017349326049957832456946207209773320943753907483088379504391317216323239870
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/59.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2033458 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2033458 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2033458 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2033458 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2033458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed

has 4 failures:

Test csrng_err has 4 failures.

18.csrng_err.10493304112465042731121861674002404510898439885886915311785498530548564615857
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2682063 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2682063 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2682063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.csrng_err.57409724458430526432204827594409829205777000901477758382583107540974592533121
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6273847 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6273847 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6273847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 3.csrng_stress_all.26068399328522160090631946130990226798473110732164108461126470911104835319734
    Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  69397062 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  69397062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.csrng_stress_all.50751858716446284158139685483134561220580395397912268401177131002787656819249
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1551437570 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1551437570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 25.csrng_stress_all.75664555139394961973286333311239716988352861487274837853333346503590976067221
    Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 438889993 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 438889993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```