CSRNG Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: `1f410ef5dc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	15.000s	17.771us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	12.157us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	36.250us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	14.000s	227.044us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	44.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	382.693us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	36.250us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.253us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	49.108us	200	200	100.00
V2	alerts	csrng_alert	19.000s	28.719us	500	500	100.00
V2	err	csrng_err	18.000s	26.558us	487	500	97.40
V2	cmds	csrng_cmds	7.133m	46.464ms	41	50	82.00
V2	life cycle	csrng_cmds	7.133m	46.464ms	41	50	82.00
V2	stress_all	csrng_stress_all	45.717m	256.891ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	16.992us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	28.612us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	910.075us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	910.075us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	12.157us	5	5	100.00
		csrng_csr_rw	5.000s	36.250us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.253us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	104.982us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	12.157us	5	5	100.00
		csrng_csr_rw	5.000s	36.250us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.253us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	104.982us	20	20	100.00
V2		TOTAL			1417	1440	98.40
V2S	tl_intg_err	csrng_sec_cm	7.000s	115.344us	5	5	100.00
		csrng_tl_intg_err	9.000s	118.158us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	23.199us	50	50	100.00
		csrng_csr_rw	5.000s	36.250us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	19.000s	28.719us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	45.717m	256.891ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	19.000s	28.719us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	45.717m	256.891ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	19.000s	28.719us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	118.158us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
		csrng_sec_cm	7.000s	115.344us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	49.108us	200	200	100.00
		csrng_err	18.000s	26.558us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	59.183m	78.684ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1597	1670	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.63	93.16	84.17	95.40	86.03	91.60	98.18	97.33	94.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 0.csrng_stress_all_with_rand_reset.96467792258403835043847565803262268891352784637085684990064086472306839878156
    Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15636944847 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15636944847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.27518465740058322506234823173890593266767006662530084420991964484391346898802
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2984422284 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2984422284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 1.csrng_stress_all_with_rand_reset.32209167497529292919354314225089055964962018848267622509251085736442476508072
    Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26096601011 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26096601011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.32736217027369312405545630396710310665144764390852959020535571637994737278519
    Line 390, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78683861073 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 78683861073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 15 failures:

Test csrng_cmds has 9 failures.

2.csrng_cmds.107199043310623120737483329530215300308364685911784374124696319384922597433326
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  2.csrng_cmds.2104041454
  
  coverage files:
    model(design data) :  /workspace/coverage/default/2.csrng_cmds.2104041454/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/2.csrng_cmds.2104041454/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 11, 2024 at 12:35:31 PDT  (total: 00:03:46)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

5.csrng_cmds.50386641474192038703907425225332064561979487176622962107206380066573391575302
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  5.csrng_cmds.1532573958
  
  coverage files:
    model(design data) :  /workspace/coverage/default/5.csrng_cmds.1532573958/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/5.csrng_cmds.1532573958/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 11, 2024 at 12:34:30 PDT  (total: 00:02:55)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 7 more failures.

Test csrng_err has 6 failures.

12.csrng_err.25144807355002465015723627422386168239814148280745706482911980802839585327452
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  12.csrng_err.1883867484
  
  coverage files:
    model(design data) :  /workspace/coverage/default/12.csrng_err.1883867484/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/12.csrng_err.1883867484/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 11, 2024 at 12:31:50 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

25.csrng_err.86180595037575329412063263278759935176071786727163736857158669409983071553290
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  25.csrng_err.661423882
  
  coverage files:
    model(design data) :  /workspace/coverage/default/25.csrng_err.661423882/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/25.csrng_err.661423882/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 11, 2024 at 12:32:19 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

158.csrng_err.39256006893743538667313811958233585385233939871186937434844261182800848082102
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/158.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2503106 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2503106 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2503106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

209.csrng_err.66314011146104361726857008905218893683785759721784545024292486471205097695321
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/209.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3571790 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3571790 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3571790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 32.csrng_stress_all.44726228136847071670554794664682001499695201550216045547783991326103818136928
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1505648351 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1505648351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 32.csrng_err.80670991145479179385964094364113647170414216327317893835031218699523311394030
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log
```
  UVM_ERROR @   2806131 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2806131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 1 failures:

Test csrng_err has 1 failures.

212.csrng_err.34378343467516702344059779229804390941546230050772825362543177119005301423697
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/212.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3765722 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3765722 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3765722 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3765722 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3765722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]