CSRNG Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	11.000s	43.473us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	22.993us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	20.113us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	11.000s	397.944us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	28.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	154.280us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	20.113us	20	20	100.00
		csrng_csr_aliasing	4.000s	28.126us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	80.073us	177	200	88.50
V2	alerts	csrng_alert	15.000s	49.052us	500	500	100.00
V2	err	csrng_err	11.000s	20.775us	486	500	97.20
V2	cmds	csrng_cmds	5.833m	27.484ms	50	50	100.00
V2	life cycle	csrng_cmds	5.833m	27.484ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.467m	58.309ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	255.747us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	48.258us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	1.055ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	1.055ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	22.993us	5	5	100.00
		csrng_csr_rw	4.000s	20.113us	20	20	100.00
		csrng_csr_aliasing	4.000s	28.126us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	111.269us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	22.993us	5	5	100.00
		csrng_csr_rw	4.000s	20.113us	20	20	100.00
		csrng_csr_aliasing	4.000s	28.126us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	111.269us	20	20	100.00
V2		TOTAL			1401	1440	97.29
V2S	tl_intg_err	csrng_sec_cm	10.000s	269.979us	5	5	100.00
		csrng_tl_intg_err	16.000s	1.411ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	11.000s	66.672us	50	50	100.00
		csrng_csr_rw	4.000s	20.113us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	15.000s	49.052us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.467m	58.309ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	15.000s	49.052us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.467m	58.309ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	15.000s	49.052us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	1.411ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
		csrng_sec_cm	10.000s	269.979us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	80.073us	177	200	88.50
		csrng_err	11.000s	20.775us	486	500	97.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.118h	167.224ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1581	1670	94.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.86	93.29	84.55	95.29	79.83	91.85	100.00	97.05	93.31

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test csrng_stress_all_with_rand_reset has 26 failures.
  - 0.csrng_stress_all_with_rand_reset.71006118974212668644166512130100818589246807623777291953225318032781132883391
    Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8462483785 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8462483785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.105757997792928050155321912544497151973440878972533075886946533647908372695450
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50686356461 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50686356461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test csrng_stress_all_with_rand_reset has 24 failures.
  - 1.csrng_stress_all_with_rand_reset.112870466854034072767070441132254433022302077125560965700068381247776429456680
    Line 354, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15917921890 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15917921890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.100459512846271291999414035852601294693416964365521513259080647833429537613182
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19220609183 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19220609183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,424): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 20 failures:

Test csrng_intr has 20 failures.

15.csrng_intr.65736196162314333842307156975285161854437143513681196177188906417598191298152
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,424): (time 54591776 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  54591776 ps: (csrng_cmd_stage.sv:424) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  54591776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.csrng_intr.98414295835808150294153307791825018254778238868567379021307211473618623552873
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,424): (time 53090105 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  53090105 ps: (csrng_cmd_stage.sv:424) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  53090105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

72.csrng_err.68274174733541921731679139719733537560725077001895834482085078394578928397437
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/72.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7913092 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7913092 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7913092 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   7913092 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   7913092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

151.csrng_err.78756055479792499980965669409452165444736177773787159454926092383771237575660
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/151.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 9298560 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 9298560 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 9298560 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   9298560 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   9298560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

26.csrng_err.22565160749870043979787004246091481331037782103591130292364027809117629708813
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 20328839 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  20328839 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  20328839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

82.csrng_err.97288903123405242103500662988115428936110258012221794489134505928244872122999
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/82.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2528115 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2528115 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2528115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1718): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

26.csrng_intr.106481989676743173805810899838746575773098507782021890154335762514959215610930
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 26858357 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 26858357 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  26858357 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  26858357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

101.csrng_intr.87144450503936724445649064354970326842804845927991247392173958373256022518815
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 21199718 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 21199718 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21199718 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21199718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 14.csrng_stress_all.115593093924814870933585484429470443759995302492586819807066734910740015095412
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 481512115 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 481512115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 34.csrng_stress_all.14494738161055406389471473786357190095811573377170198895471066339752960662775
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 20923911643 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 20923911643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```