CSRNG Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	19.000s	23.937us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	58.550us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	84.589us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	332.456us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	87.756us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	487.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	84.589us	20	20	100.00
		csrng_csr_aliasing	4.000s	87.756us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	50.732us	181	200	90.50
V2	alerts	csrng_alert	22.000s	39.267us	500	500	100.00
V2	err	csrng_err	21.000s	21.824us	492	500	98.40
V2	cmds	csrng_cmds	11.600m	73.842ms	50	50	100.00
V2	life cycle	csrng_cmds	11.600m	73.842ms	50	50	100.00
V2	stress_all	csrng_stress_all	36.050m	187.532ms	48	50	96.00
V2	intr_test	csrng_intr_test	13.000s	32.637us	50	50	100.00
V2	alert_test	csrng_alert_test	16.000s	70.886us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	558.451us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	558.451us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	58.550us	5	5	100.00
		csrng_csr_rw	4.000s	84.589us	20	20	100.00
		csrng_csr_aliasing	4.000s	87.756us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	34.038us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	58.550us	5	5	100.00
		csrng_csr_rw	4.000s	84.589us	20	20	100.00
		csrng_csr_aliasing	4.000s	87.756us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	34.038us	20	20	100.00
V2		TOTAL			1411	1440	97.99
V2S	tl_intg_err	csrng_sec_cm	9.000s	314.682us	5	5	100.00
		csrng_tl_intg_err	13.000s	930.465us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	14.000s	40.172us	50	50	100.00
		csrng_csr_rw	4.000s	84.589us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	22.000s	39.267us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	36.050m	187.532ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	22.000s	39.267us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	36.050m	187.532ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	22.000s	39.267us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	930.465us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
		csrng_sec_cm	9.000s	314.682us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	50.732us	181	200	90.50
		csrng_err	21.000s	21.824us	492	500	98.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	39.583m	37.847ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1591	1670	95.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.89	93.33	84.64	95.35	79.87	91.85	100.00	97.38	92.54

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test csrng_stress_all_with_rand_reset has 27 failures.
  - 0.csrng_stress_all_with_rand_reset.95090528843700621576842956781551628194662596174155267800047421443702664832586
    Line 405, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9291822577 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9291822577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.69349689830494893629026274752638785107303993034365088658699632505455875427662
    Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2855516682 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2855516682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test csrng_stress_all_with_rand_reset has 23 failures.
  - 3.csrng_stress_all_with_rand_reset.59445991644906754365558512223244163194602498894986358041784081925177688822961
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 355199078 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 355199078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.16370881233180721655397552553108319670822236168067929304302922398617005004650
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103055187 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 103055187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,424): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 15 failures:

Test csrng_intr has 15 failures.

20.csrng_intr.67849820619391598491371123523302040019655695779850443261262336168067686545473
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,424): (time 70734751 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  70734751 ps: (csrng_cmd_stage.sv:424) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  70734751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.csrng_intr.78277045179344774735253243111568256651012771036351029084192019647521091656449
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,424): (time 17871444 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  17871444 ps: (csrng_cmd_stage.sv:424) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  17871444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

3.csrng_err.4647031241516052509911736964856829380065061606760130986583754038025329003256
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2153311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2153311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2153311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2153311 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2153311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

105.csrng_err.28937522794209628419052721872858746961252817007224377135444954435718421171476
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/105.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6643751 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6643751 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6643751 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   6643751 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   6643751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1718): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

34.csrng_intr.86374650682853009511809468307904920381172995027668898106605376058320030325112
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 55405146 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 55405146 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  55405146 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  55405146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

89.csrng_intr.97415783300478475245211476228147496061601247076623256187155781225145994788884
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1718): (time 45268479 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1719): (time 45268479 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  45268479 ps: (csrng_core.sv:1718) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  45268479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

161.csrng_err.58992420755648669884194980312092913418355282460640524897688966754853133548641
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/161.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1736621 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1736621 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1736621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

291.csrng_err.106014314408056644018038167789513080810594443079680187983584036371114592225077
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/291.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2481770 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2481770 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2481770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.9864747921953221587149629721375390946429746836686965697463778290468950894907
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  12845994 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  12845994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 33.csrng_stress_all.89510556401860148564210670820892328735806808243180124250194290363332188373104
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1885091239 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1885091239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 333.csrng_err.35703990843645578419332157970359171794690135668961054682566505035067383039363
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/333.csrng_err/latest/run.log
```
  UVM_ERROR @  14639439 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  14639439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```