CSRNG Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	16.000s	38.502us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	24.190us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	25.957us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	881.110us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	40.483us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	174.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	25.957us	20	20	100.00
		csrng_csr_aliasing	5.000s	40.483us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	59.002us	178	200	89.00
V2	alerts	csrng_alert	25.000s	29.932us	500	500	100.00
V2	err	csrng_err	23.000s	26.632us	494	500	98.80
V2	cmds	csrng_cmds	8.133m	49.801ms	50	50	100.00
V2	life cycle	csrng_cmds	8.133m	49.801ms	50	50	100.00
V2	stress_all	csrng_stress_all	16.800m	68.167ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	194.531us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	55.817us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	557.274us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	557.274us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	24.190us	5	5	100.00
		csrng_csr_rw	4.000s	25.957us	20	20	100.00
		csrng_csr_aliasing	5.000s	40.483us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	130.691us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	24.190us	5	5	100.00
		csrng_csr_rw	4.000s	25.957us	20	20	100.00
		csrng_csr_aliasing	5.000s	40.483us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	130.691us	20	20	100.00
V2		TOTAL			1411	1440	97.99
V2S	tl_intg_err	csrng_sec_cm	8.000s	298.725us	5	5	100.00
		csrng_tl_intg_err	17.000s	1.814ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	12.652us	50	50	100.00
		csrng_csr_rw	4.000s	25.957us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	25.000s	29.932us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	16.800m	68.167ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	25.000s	29.932us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	16.800m	68.167ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	25.000s	29.932us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	1.814ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
		csrng_sec_cm	8.000s	298.725us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	59.002us	178	200	89.00
		csrng_err	23.000s	26.632us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.143h	44.524ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1591	1670	95.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.81	93.24	84.51	95.22	80.12	91.81	100.00	97.55	92.54

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 1.csrng_stress_all_with_rand_reset.66747171505356123715818103759824650852286645339320244876960797819046406253683
    Line 374, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7562005298 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7562005298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.100199036203430621588683963624323833652702380441931800851098268461029149964140
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7574043339 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7574043339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 0.csrng_stress_all_with_rand_reset.100553030887144668359705428059435231580905969548481039471855535024417873515119
    Line 402, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25737769588 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25737769588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.33268249073124266291758089068759814150676842178951915630115858096542419915378
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110023358 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 110023358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,440): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 20 failures:

Test csrng_intr has 20 failures.

8.csrng_intr.41005307371111812120672292269002716115846049656396699997274836087992453602166
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,440): (time 31224951 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  31224951 ps: (csrng_cmd_stage.sv:440) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  31224951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.csrng_intr.84770331533828983772364177622378584126729579121689826348015900301076874057753
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,440): (time 192592096 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 192592096 ps: (csrng_cmd_stage.sv:440) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 192592096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

157.csrng_err.26660031216153966253151202926156897041965076341559214125142816028856097214645
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/157.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3388948 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3388948 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3388948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

214.csrng_err.15029444856085808057827517576477628915509895658530308615796235753005230070103
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/214.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 8946833 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8946833 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8946833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1737): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

51.csrng_intr.28089929430459153673458483630239151218232506082850199252300550800309697725808
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/51.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1737): (time 30330262 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1738): (time 30330262 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  30330262 ps: (csrng_core.sv:1737) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  30330262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

109.csrng_intr.4519235494300403356595436126366207661822080538271756402112167367914153179592
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/109.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1737): (time 15134502 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1738): (time 15134502 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15134502 ps: (csrng_core.sv:1737) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15134502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.98615480433493723713511983155158161008375642689954267363022689546681717840296
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  37708216 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  37708216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 1 failures:

Test csrng_err has 1 failures.

109.csrng_err.96128589637482165323830616656994405842297427636402064526630367939508470016550
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/109.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 16288853 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 16288853 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 16288853 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  16288853 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  16288853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]