CSRNG Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	31.286us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	23.336us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	22.332us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.100m	3.778ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	89.458us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	402.391us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	22.332us	20	20	100.00
		csrng_csr_aliasing	12.000s	89.458us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	33.455us	196	200	98.00
V2	alerts	csrng_alert	1.600m	7.625ms	500	500	100.00
V2	err	csrng_err	24.000s	49.566us	446	500	89.20
V2	cmds	csrng_cmds	8.417m	24.858ms	50	50	100.00
V2	life cycle	csrng_cmds	8.417m	24.858ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.400m	46.511ms	47	50	94.00
V2	intr_test	csrng_intr_test	9.000s	54.949us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	15.233us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	556.669us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	556.669us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	23.336us	5	5	100.00
		csrng_csr_rw	8.000s	22.332us	20	20	100.00
		csrng_csr_aliasing	12.000s	89.458us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	32.951us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	23.336us	5	5	100.00
		csrng_csr_rw	8.000s	22.332us	20	20	100.00
		csrng_csr_aliasing	12.000s	89.458us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	32.951us	20	20	100.00
V2		TOTAL			1379	1440	95.76
V2S	tl_intg_err	csrng_sec_cm	8.000s	313.034us	5	5	100.00
		csrng_tl_intg_err	13.000s	509.313us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	31.958us	50	50	100.00
		csrng_csr_rw	8.000s	22.332us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.600m	7.625ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.400m	46.511ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.600m	7.625ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.400m	46.511ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.600m	7.625ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	509.313us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
		csrng_sec_cm	8.000s	313.034us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	33.455us	196	200	98.00
		csrng_err	24.000s	49.566us	446	500	89.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	55.600m	151.938ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1559	1670	93.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.06	93.54	85.33	95.42	81.25	91.84	100.00	97.58	89.85

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test csrng_stress_all_with_rand_reset has 34 failures.
  - 1.csrng_stress_all_with_rand_reset.7207543086985414129741411825535131132485211449027097035508591130191978622644
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8323329940 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8323329940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.64179621165071223843007909863118956603446355262357459633275836833303164682990
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4401946843 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4401946843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.intr_state reset value: * has 30 failures:
- Test csrng_err has 30 failures.
  - 1.csrng_err.24713458782740017457045554437681735599432506722837693000206597592827246408469
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_err/latest/run.log
```
  UVM_ERROR @  73464820 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
  UVM_INFO @  73464820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.csrng_err.92921966722003188362837917446537490413098170567376488308172563946388969992219
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/53.csrng_err/latest/run.log
```
  UVM_ERROR @  11677837 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
  UVM_INFO @  11677837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test csrng_stress_all_with_rand_reset has 16 failures.
  - 0.csrng_stress_all_with_rand_reset.10965858282298850019333740250916052341987908081737456666881811475318311919916
    Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3219285603 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3219285603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.106278486002575480951709916288367892303151608181710854362287858481108831258547
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 470383923 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 470383923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 12 failures:

Test csrng_err has 12 failures.

142.csrng_err.18193047010433447897910612849636096324676526993810617568479838698291047627140
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/142.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3252708 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3252708 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3252708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

143.csrng_err.110659939411261139586158471608363043974165398917434972206970814186699993697878
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/143.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3038457 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3038457 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3038457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

83.csrng_err.96630900455397177495255409730853987362799985231050960306693326437575732844228
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/83.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1585757 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1585757 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1585757 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1585757 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1585757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

89.csrng_err.97496740671085549374425821437933228085372588981285602806425847776274171986819
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2539834 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2539834 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2539834 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2539834 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2539834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

120.csrng_err.59725253668669955184057858431024447890924579268588593360001571402462156434062
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/120.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  120.csrng_err.2516724366
  
  coverage files:
    model(design data) :  /workspace/coverage/default/120.csrng_err.2516724366/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/120.csrng_err.2516724366/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 10, 2024 at 16:46:39 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

166.csrng_err.91896979267394716086706148802112376066002819031062452348494531504139363660467
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/166.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  166.csrng_err.3085152947
  
  coverage files:
    model(design data) :  /workspace/coverage/default/166.csrng_err.3085152947/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/166.csrng_err.3085152947/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 10, 2024 at 16:47:10 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1766): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

10.csrng_intr.32350263778599456457973771921091322510302446527149256820087655975208591320704
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1766): (time 214033808 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 214033808 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 214033808 ps: (csrng_core.sv:1766) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 214033808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

62.csrng_intr.104953398822806925236911145137289654478366022321875446742093664026861429487675
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/62.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1766): (time 10701355 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 10701355 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  10701355 ps: (csrng_core.sv:1766) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  10701355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 30.csrng_stress_all.10062724996611172257409073856551243150419338746559837527641129647024910176431
    Line 327, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3051410166 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3051410166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.csrng_stress_all.78686201327297468669600535969157405426377035983292628242311806039031885759729
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3695094200 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3695094200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

20.csrng_err.99456931863238293467367364538185738712401195597288577799681033467892792652610
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_err/latest/run.log

  UVM_ERROR @  11615344 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11615344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

344.csrng_err.46954541844134486768822091816751781245700505823094721971401896335853555026159
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/344.csrng_err/latest/run.log

  UVM_ERROR @   3445774 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3445774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1765): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

76.csrng_intr.33618349754044783212117174331013858403133082195326334772365295446272553511001
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/76.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1765): (time 15993172 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1766): (time 15993172 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 15993172 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 15993172 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 15993172 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed