CSRNG Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	21.730us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	13.614us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	84.720us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	2.559ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	148.143us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	208.232us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	84.720us	20	20	100.00
		csrng_csr_aliasing	6.000s	148.143us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	50.625us	192	200	96.00
V2	alerts	csrng_alert	55.000s	2.663ms	500	500	100.00
V2	err	csrng_err	29.000s	10.879us	481	500	96.20
V2	cmds	csrng_cmds	6.950m	26.621ms	50	50	100.00
V2	life cycle	csrng_cmds	6.950m	26.621ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.667m	151.986ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	18.201us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	10.562us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	355.897us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	355.897us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	13.614us	5	5	100.00
		csrng_csr_rw	4.000s	84.720us	20	20	100.00
		csrng_csr_aliasing	6.000s	148.143us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	36.416us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	13.614us	5	5	100.00
		csrng_csr_rw	4.000s	84.720us	20	20	100.00
		csrng_csr_aliasing	6.000s	148.143us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	36.416us	20	20	100.00
V2		TOTAL			1411	1440	97.99
V2S	tl_intg_err	csrng_sec_cm	6.000s	177.539us	5	5	100.00
		csrng_tl_intg_err	17.000s	397.675us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	39.897us	50	50	100.00
		csrng_csr_rw	4.000s	84.720us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	55.000s	2.663ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.667m	151.986ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	55.000s	2.663ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.667m	151.986ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	55.000s	2.663ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	397.675us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
		csrng_sec_cm	6.000s	177.539us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	50.625us	192	200	96.00
		csrng_err	29.000s	10.879us	481	500	96.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.556h	354.055ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1591	1670	95.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.95	93.41	85.05	95.34	80.56	91.81	100.00	97.55	90.81

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
- Test csrng_stress_all_with_rand_reset has 34 failures.
  - 4.csrng_stress_all_with_rand_reset.82521953695041725444697348107426911048006610893013400482182686765605576991720
    Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24410869880 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24410869880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.25512200970126707119236913376164703564822495058160002403458273477103685070614
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 553981807 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 553981807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 32 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test csrng_stress_all_with_rand_reset has 16 failures.
  - 0.csrng_stress_all_with_rand_reset.56503649115670736003302081877735028452962057065843308279815701989188302886149
    Line 394, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8812434521 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8812434521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.29555215894592283244405637404947385368530653568981568286352480209191144888835
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1272262236 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1272262236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 10 failures:

Test csrng_err has 10 failures.

15.csrng_err.27404410777375535477599192332880342384156223212591906557122315719989648104969
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 5008466 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   5008466 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5008466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

69.csrng_err.80615410289207794749813845499374270799415020404985420129402896627907061534532
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/69.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2246618 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2246618 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2246618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 7 failures:

Test csrng_intr has 7 failures.

13.csrng_intr.71125104168130888677703454220230960705067128992894335494006436916234636250233
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 27183436 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  27183436 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  27183436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.csrng_intr.82535881927554367493270869270534897134005052056682631468351874480940125049359
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 75707483 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  75707483 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  75707483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

131.csrng_err.78215667906576385563963721299341567972560411483328346138554044800434167993919
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/131.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 19479020 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 19479020 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 19479020 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  19479020 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  19479020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

146.csrng_err.82576915218581848703216090543947695106909435561248979398776902267352506776468
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/146.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2888455 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2888455 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2888455 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2888455 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2888455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

27.csrng_err.49065405492194593837922302443896896501010734077371360662266610701278728913903
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  27.csrng_err.1311474671
  
  coverage files:
    model(design data) :  /workspace/coverage/default/27.csrng_err.1311474671/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/27.csrng_err.1311474671/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 02, 2024 at 12:33:33 PDT  (total: 00:00:08)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

248.csrng_err.48892374941921595644827429723468363915872173675893507841651658586772159708932
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/248.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  248.csrng_err.4198874884
  
  coverage files:
    model(design data) :  /workspace/coverage/default/248.csrng_err.4198874884/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/248.csrng_err.4198874884/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 02, 2024 at 12:35:14 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 28.csrng_stress_all.103030892896920770916739850476538812639755343148228774949129251937335180574746
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 101829491288 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 101829491288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 39.csrng_stress_all.15654833040871734178348992165825180270274039289740757874444641817631711100307
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7454993603 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7454993603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 1 failures:

Test csrng_intr has 1 failures.

87.csrng_intr.57947870962317610089622923112278640791961913220146158423379028203419644358950
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 21116308 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 21116308 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21116308 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21116308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 174.csrng_err.58320617622957546830468501824258180470397701728081145251341250924653305434040
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/174.csrng_err/latest/run.log
```
  UVM_ERROR @  36059357 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  36059357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```