CSRNG Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	40.323us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	37.862us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	40.464us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	649.706us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	96.223us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	13.000s	23.867us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	40.464us	20	20	100.00
		csrng_csr_aliasing	7.000s	96.223us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	16.000s	29.077us	200	200	100.00
V2	alerts	csrng_alert	1.167m	5.519ms	500	500	100.00
V2	err	csrng_err	18.000s	38.549us	460	500	92.00
V2	cmds	csrng_cmds	8.183m	41.724ms	45	50	90.00
V2	life cycle	csrng_cmds	8.183m	41.724ms	45	50	90.00
V2	stress_all	csrng_stress_all	21.700m	75.944ms	31	50	62.00
V2	intr_test	csrng_intr_test	13.000s	55.384us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	14.459us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	649.988us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	649.988us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	37.862us	5	5	100.00
		csrng_csr_rw	8.000s	40.464us	20	20	100.00
		csrng_csr_aliasing	7.000s	96.223us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	191.057us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	37.862us	5	5	100.00
		csrng_csr_rw	8.000s	40.464us	20	20	100.00
		csrng_csr_aliasing	7.000s	96.223us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	191.057us	20	20	100.00
V2		TOTAL			1376	1440	95.56
V2S	tl_intg_err	csrng_sec_cm	7.000s	228.017us	5	5	100.00
		csrng_tl_intg_err	16.000s	355.654us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	41.495us	50	50	100.00
		csrng_csr_rw	8.000s	40.464us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	5.519ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.700m	75.944ms	31	50	62.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	5.519ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.700m	75.944ms	31	50	62.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	5.519ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	355.654us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
		csrng_sec_cm	7.000s	228.017us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	16.000s	29.077us	200	200	100.00
		csrng_err	18.000s	38.549us	460	500	92.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.625h	185.015ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1556	1670	93.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.99	93.46	85.09	95.35	81.19	91.90	100.00	97.58	89.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 2.csrng_stress_all_with_rand_reset.71709860643701592258094201140230089897258524796078650327541218886390946995684
    Line 380, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30497291863 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30497291863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.21631862984470754581970710083749223669428771966868642249947855508673392690192
    Line 868, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 185015461439 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 185015461439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.intr_state reset value: * has 24 failures:
- Test csrng_err has 24 failures.
  - 2.csrng_err.99207290162513963426594537866021706835091175155392106977478393271055280634601
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_err/latest/run.log
```
  UVM_ERROR @   3894593 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
  UVM_INFO @   3894593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_err.110900484908274669798416688636183263760380263229559736808251272994733974436195
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_err/latest/run.log
```
  UVM_ERROR @  29292231 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
  UVM_INFO @  29292231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 0.csrng_stress_all_with_rand_reset.20103031731483421830355130106089235430538503501911156210568542296702843856516
    Line 378, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15292154716 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15292154716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.83046116036013533299928261322476030926173113805166430785820031749334247654966
    Line 543, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 231374962342 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 231374962342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

UVM_FATAL (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (* [*] vs * [*])

has 19 failures:

Test csrng_stress_all has 14 failures.

0.csrng_stress_all.84500413009759151831953909572509716159622179503663066890975465198359623869314
Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

  UVM_FATAL @ 3387158025 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 3387158025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.csrng_stress_all.100676499759624592471592222175763386117802835319044857644396052719303212640413
Line 307, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log

  UVM_FATAL @ 3410879911 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 3410879911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test csrng_cmds has 5 failures.

2.csrng_cmds.12903817003280916731430447580730489771907814854549072064331070330058603221271
Line 366, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_cmds/latest/run.log

  UVM_FATAL @ 868388074 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 868388074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.csrng_cmds.53560274456125989742865134272401817934210554330600412049573558517121424214948
Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_cmds/latest/run.log

  UVM_FATAL @ 10507231685 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 10507231685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 7 failures:

Test csrng_err has 7 failures.

55.csrng_err.9982299776120505250998763973886593763433826791339858647722102668118651645616
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/55.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2037801 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2037801 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2037801 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2037801 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2037801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

199.csrng_err.99745873804403766753445066657276694825626881490910669811753510628257563111763
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/199.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3469646 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3469646 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3469646 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3469646 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3469646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

88.csrng_err.64144496062635730552324780910679572169645384748832884096955685196631135083533
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/88.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  88.csrng_err.2317736973
  
  coverage files:
    model(design data) :  /workspace/coverage/default/88.csrng_err.2317736973/icc_7963752d_251369e9.ucm
    data               :  /workspace/coverage/default/88.csrng_err.2317736973/icc_7963752d_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 07, 2024 at 18:09:54 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

164.csrng_err.115463483729594508780476681910906520169275832552722570968914104170385091913792
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/164.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  164.csrng_err.160229440
  
  coverage files:
    model(design data) :  /workspace/coverage/default/164.csrng_err.160229440/icc_7963752d_251369e9.ucm
    data               :  /workspace/coverage/default/164.csrng_err.160229440/icc_7963752d_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 07, 2024 at 18:10:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed

has 4 failures:

Test csrng_err has 4 failures.

160.csrng_err.21880356394735187553673232045675091406690127083552002907330531270583670154606
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/160.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 7621637 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7621637 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7621637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

206.csrng_err.24420399270168783168008244893098604984342205107662128532996133015712736933255
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/206.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1704126 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1704126 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1704126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 21.csrng_stress_all.85679792145907157668115604038766092379695336125269848766154216124649773608751
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 67659079497 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 67659079497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all.26597030339871951353265589272040447738720807858580453326814174012391314809132
    Line 328, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7256185740 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7256185740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 13.csrng_stress_all.57175438239446390370544802213364291596409328744146722935477498990091278308188
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 15854304160 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 15854304160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.csrng_stress_all.99294907813817841636423294341928390242476440851610085079700368075308750202586
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  18109116 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  18109116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```