CSRNG Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	24.693us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	13.103us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	78.857us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	24.000s	1.027ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	92.984us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	82.314us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	78.857us	20	20	100.00
		csrng_csr_aliasing	6.000s	92.984us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	34.093us	174	200	87.00
V2	alerts	csrng_alert	1.083m	5.159ms	500	500	100.00
V2	err	csrng_err	20.000s	27.735us	485	500	97.00
V2	cmds	csrng_cmds	7.433m	43.118ms	49	50	98.00
V2	life cycle	csrng_cmds	7.433m	43.118ms	49	50	98.00
V2	stress_all	csrng_stress_all	19.850m	40.287ms	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	156.931us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	29.433us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	479.142us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	479.142us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	13.103us	5	5	100.00
		csrng_csr_rw	4.000s	78.857us	20	20	100.00
		csrng_csr_aliasing	6.000s	92.984us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	37.688us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	13.103us	5	5	100.00
		csrng_csr_rw	4.000s	78.857us	20	20	100.00
		csrng_csr_aliasing	6.000s	92.984us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	37.688us	20	20	100.00
V2		TOTAL			1398	1440	97.08
V2S	tl_intg_err	csrng_sec_cm	10.000s	158.147us	5	5	100.00
		csrng_tl_intg_err	11.000s	561.400us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	18.000s	43.836us	50	50	100.00
		csrng_csr_rw	4.000s	78.857us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	5.159ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.850m	40.287ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	5.159ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.850m	40.287ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	5.159ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	561.400us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
		csrng_sec_cm	10.000s	158.147us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	34.093us	174	200	87.00
		csrng_err	20.000s	27.735us	485	500	97.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.570h	187.182ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1578	1670	94.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.96	93.45	85.11	95.35	80.78	91.81	100.00	97.56	89.83

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test csrng_stress_all_with_rand_reset has 32 failures.
  - 3.csrng_stress_all_with_rand_reset.77363398465944907710205021437340407945056321616258997736099216327981523269225
    Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 218488751 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 218488751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.77851205930392770542996431387387736402255610971405852918406269808748994797633
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2921862627 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2921862627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed

has 22 failures:

Test csrng_intr has 22 failures.

2.csrng_intr.12080551146362524862753070098340684012520851929660083679788929954848570524219
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 15574379 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  15574379 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  15574379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.csrng_intr.19812663518378510309367065492718699952799794238515079038603554008039325879706
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 34572613 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  34572613 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  34572613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 1.csrng_stress_all_with_rand_reset.28783674852123378748686136542101889348574199476290188091483767525539009166005
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18857042891 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18857042891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.35519161950157814075709696584682819443474443455926669292267138554269767282072
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2093687494 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2093687494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed

has 6 failures:

Test csrng_err has 6 failures.

18.csrng_err.114065261174246160711553487276841243251509778338135447263663201227024456655973
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1830818 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1830818 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1830818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

70.csrng_err.30483010175626904808200319529492341690332427983067639400464634636252933591682
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/70.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6716004 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6716004 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6716004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

138.csrng_err.103336987578286674627307816048015239492237305042732255674881718967106267653821
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/138.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  138.csrng_err.2376738493
  
  coverage files:
    model(design data) :  /workspace/coverage/default/138.csrng_err.2376738493/icc_3aaab549_5871fdb4.ucm
    data               :  /workspace/coverage/default/138.csrng_err.2376738493/icc_3aaab549_5871fdb4.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 05, 2024 at 15:40:12 PDT  (total: 00:00:06)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

231.csrng_err.98909761798811654488773931302622340773153372125207402053419420695751570048071
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/231.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  231.csrng_err.1487225927
  
  coverage files:
    model(design data) :  /workspace/coverage/default/231.csrng_err.1487225927/icc_3aaab549_5871fdb4.ucm
    data               :  /workspace/coverage/default/231.csrng_err.1487225927/icc_3aaab549_5871fdb4.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 05, 2024 at 15:41:36 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1748): Assertion CsrngUniZeroizeKey_A has failed

has 4 failures:

Test csrng_intr has 4 failures.

64.csrng_intr.60385587921292302077209977215665478826789763391678635774408347351517124786922
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/64.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1748): (time 15753924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1749): (time 15753924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15753924 ps: (csrng_core.sv:1748) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15753924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

91.csrng_intr.105684385865781279318521011752373421087246296121452615221503149412472122408818
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/91.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1748): (time 42573576 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1749): (time 42573576 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  42573576 ps: (csrng_core.sv:1748) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  42573576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 4 failures:

Test csrng_err has 4 failures.

136.csrng_err.34010615153538731779799992823318125494715155668657356379344477520798102288336
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/136.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3651792 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3651792 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3651792 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3651792 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3651792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

267.csrng_err.115112795148684738512977468888828561495039783355646735189476365457561250723232
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/267.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4943909 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4943909 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4943909 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4943909 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4943909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:370) scoreboard [scoreboard] invalid csr: csrng_reg_block.fips_force has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.107358357174340542395044065641554183161146673532004707425387693917923629666639
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  24779271 ps: (csrng_scoreboard.sv:370) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: csrng_reg_block.fips_force
  UVM_INFO @  24779271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.csrng_stress_all_with_rand_reset.35142835941695766808681210353144665585833408924699349876013144133410632895104
    Line 375, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7495804457 ps: (csrng_scoreboard.sv:370) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: csrng_reg_block.fips_force
  UVM_INFO @ 7495804457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 46.csrng_cmds.16491881927130515864794176330424519461432653305680419692634596289330655440640
    Line 374, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 3256706616 ps: (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3256706616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```