CSRNG Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	18.341us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	42.684us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	85.430us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	36.000s	1.608ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	33.611us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	263.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	85.430us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.611us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	11.000s	218.052us	180	200	90.00
V2	alerts	csrng_alert	1.233m	5.004ms	500	500	100.00
V2	err	csrng_err	14.000s	68.453us	493	500	98.60
V2	cmds	csrng_cmds	10.450m	57.887ms	35	50	70.00
V2	life cycle	csrng_cmds	10.450m	57.887ms	35	50	70.00
V2	stress_all	csrng_stress_all	19.500m	42.181ms	41	50	82.00
V2	intr_test	csrng_intr_test	4.000s	63.158us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	54.082us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	616.198us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	616.198us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	42.684us	5	5	100.00
		csrng_csr_rw	4.000s	85.430us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.611us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	531.052us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	42.684us	5	5	100.00
		csrng_csr_rw	4.000s	85.430us	20	20	100.00
		csrng_csr_aliasing	5.000s	33.611us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	531.052us	20	20	100.00
V2		TOTAL			1389	1440	96.46
V2S	tl_intg_err	csrng_sec_cm	8.000s	708.023us	5	5	100.00
		csrng_tl_intg_err	14.000s	238.831us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	20.363us	50	50	100.00
		csrng_csr_rw	4.000s	85.430us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.233m	5.004ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.500m	42.181ms	41	50	82.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.233m	5.004ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.500m	42.181ms	41	50	82.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.233m	5.004ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	238.831us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
		csrng_sec_cm	8.000s	708.023us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	11.000s	218.052us	180	200	90.00
		csrng_err	14.000s	68.453us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.381h	289.300ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1569	1670	93.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.00	93.48	85.19	95.39	80.78	91.87	98.18	97.56	90.04

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 0.csrng_stress_all_with_rand_reset.75292455395489708513833333652756137329438812699902139447046049105789038114633
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10020041146 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10020041146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.49238925681440665820022514842920908479701201920838823840765145676493783993690
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3190324023 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3190324023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 4.csrng_stress_all_with_rand_reset.60549790204424830199228694228658632417408309677076463823127655403733323897762
    Line 387, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17189917257 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17189917257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.112351035965464580080729720170115552886934567368820058608135472215572399643116
    Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22495069537 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22495069537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

UVM_FATAL (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (* [*] vs * [*]) has 20 failures:

Test csrng_cmds has 13 failures.

1.csrng_cmds.66864333872579190221160485157778557363121249048106668789946715603591936301482
Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_cmds/latest/run.log

  UVM_FATAL @ 645143579 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 645143579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.csrng_cmds.79928344236126242495204957606772931425092645885817447797576394518049424367757
Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_cmds/latest/run.log

  UVM_FATAL @ 593264508 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 593264508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test csrng_stress_all has 7 failures.

1.csrng_stress_all.18579851306838706089668156781267617443933226760873705678028160611951642186830
Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log

  UVM_FATAL @ 192060726 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 192060726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.csrng_stress_all.109405792153593454297308208431245504656889373389393205749411964647459821754423
Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log

  UVM_FATAL @ 1190008420 ps: (csrng_env_cfg.sv:290) [cfg] Check failed {hw_compliance, hw_status} == {compliance[app], status[app]} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 1190008420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 19 failures:

Test csrng_intr has 19 failures.

39.csrng_intr.76562563866278913374219276908698493632806819008151728685649976725003565316985
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 37266694 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  37266694 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  37266694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.csrng_intr.105437949415550774344818432400968770734858816804583617559991481863486525400276
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 65526928 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  65526928 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  65526928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

156.csrng_err.34690577991124184455951739211036049933272801822578442406912663770342638267871
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/156.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 10139900 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  10139900 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10139900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

313.csrng_err.109688416413314311118882405367729643779947722734513626306688138266036895139064
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/313.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 1721461 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1721461 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1721461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 18.csrng_stress_all.84804872161834112967042358833437633239011514941103922292334912581882313258484
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 223807651 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 223807651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.csrng_stress_all.90671780529804253270071406586908425835962895122853914551391725196091114406200
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 42180964531 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 42180964531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

82.csrng_err.5361324524532866736584994023313651136525602783807236607056352991650216406238
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/82.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 11620152 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 11620152 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 11620152 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  11620152 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  11620152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

385.csrng_err.28922910633175859169161574886216530659174786233824388340643050791361621795939
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/385.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1416199 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1416199 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1416199 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1416199 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1416199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

221.csrng_err.96173503528676765418813860481877381547085689006423588539548335331611138208336
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/221.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  221.csrng_err.2362061392
  
  coverage files:
    model(design data) :  /workspace/coverage/default/221.csrng_err.2362061392/icc_3aaab549_5871fdb4.ucm
    data               :  /workspace/coverage/default/221.csrng_err.2362061392/icc_3aaab549_5871fdb4.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 06, 2024 at 14:29:44 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

250.csrng_err.56050030565005957795560102851222233735939692144207722732731843122545916357989
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/250.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  250.csrng_err.1099148645
  
  coverage files:
    model(design data) :  /workspace/coverage/default/250.csrng_err.1099148645/icc_3aaab549_5871fdb4.ucm
    data               :  /workspace/coverage/default/250.csrng_err.1099148645/icc_3aaab549_5871fdb4.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 06, 2024 at 14:29:35 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1748): Assertion CsrngUniZeroizeKey_A has failed has 1 failures:

Test csrng_intr has 1 failures.

3.csrng_intr.13533979444439420132298978439758286467009227546068217716526135291067704813752
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1748): (time 101805113 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1749): (time 101805113 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1750): (time 101805113 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1751): (time 101805113 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 101805113 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed

UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 23.csrng_cmds.39906164481252522347808504604213357231623741121273731173076588926044091990072
    Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 185298709 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (91428839180889021635359265862925019043 [0x44c88dcd6ec409b8530a19688cbde7a3] vs 0 [0x0])
  UVM_INFO @ 185298709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 42.csrng_cmds.31587790599865253688007393651373340687792299837334033836323010667076418891106
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 541525581 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (5 [0x5] vs 0 [0x0])
  UVM_INFO @ 541525581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```