dd5ad5fb77| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 9.000s | 80.384us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 197.839us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 4.000s | 87.317us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 49.000s | 2.157ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 7.000s | 77.055us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 5.000s | 32.203us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 87.317us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 7.000s | 77.055us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| V2 | alerts | csrng_alert | 56.000s | 4.323ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 |
| V2 | cmds | csrng_cmds | 11.267m | 57.275ms | 48 | 50 | 96.00 |
| V2 | life cycle | csrng_cmds | 11.267m | 57.275ms | 48 | 50 | 96.00 |
| V2 | stress_all | csrng_stress_all | 24.933m | 91.457ms | 49 | 50 | 98.00 |
| V2 | intr_test | csrng_intr_test | 4.000s | 133.080us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 4.000s | 43.706us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 36.000s | 2.812ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 36.000s | 2.812ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 197.839us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 87.317us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 77.055us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 10.000s | 607.765us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 197.839us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 87.317us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 7.000s | 77.055us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 10.000s | 607.765us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1395 | 1440 | 96.88 | |||
| V2S | tl_intg_err | csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 18.000s | 317.410us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 8.000s | 57.939us | 50 | 50 | 100.00 |
| csrng_csr_rw | 4.000s | 87.317us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 56.000s | 4.323ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 24.933m | 91.457ms | 49 | 50 | 98.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 56.000s | 4.323ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 24.933m | 91.457ms | 49 | 50 | 98.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 56.000s | 4.323ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 18.000s | 317.410us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| csrng_sec_cm | 11.000s | 1.124ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 8.000s | 403.424us | 199 | 200 | 99.50 |
| csrng_err | 8.000s | 23.475us | 459 | 500 | 91.80 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.459h | 104.877ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1575 | 1670 | 94.31 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 5 | 55.56 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.07 | 93.54 | 85.33 | 95.43 | 81.22 | 91.90 | 100.00 | 97.58 | 89.85 |
UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
1.csrng_stress_all_with_rand_reset.115435358369045573683719533855544408669334858453304679163455372451273575875223
Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15921064299 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15921064299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.csrng_stress_all_with_rand_reset.71158873720050745867127285908825197026636142033715811441324615252632945218292
Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17866112109 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17866112109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.intr_state reset value: * has 23 failures:
35.csrng_err.113911434912764509540892585226388930801375468510293916688348678677621975248422
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_err/latest/run.log
UVM_ERROR @ 4241955 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
UVM_INFO @ 4241955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.csrng_err.112994084891692429705750403740086273905632091859733719595149805429281752228756
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_err/latest/run.log
UVM_ERROR @ 14781670 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: csrng_reg_block.intr_state reset value: 0x0
UVM_INFO @ 14781670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.csrng_stress_all_with_rand_reset.112653934745772366938906083982684717408091038598857284047084502788095787138649
Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32167677607 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 32167677607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.32597438581978740509546779239805304977303034900692103651426984601392077056988
Line 416, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19680959829 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19680959829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:
20.csrng_err.105506777518730805160198289786767925574910033515392452205723359967586107188639
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 7582830 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 7582830 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 7582830 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 7582830 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 7582830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
93.csrng_err.105727927198282706367441739953996004849152617411832013063841517826958517094478
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/93.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2442980 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2442980 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2442980 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 2442980 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 2442980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 7 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:
17.csrng_err.32707926005218114734964875605731915508274286531009718156454481951605582294247
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2278768 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2278768 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2278768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.csrng_err.75389036190450524581288350217094147307458946841421162051069553208567064484749
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 11704055 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 11704055 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 11704055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
140.csrng_err.52590432889237683952749929161590689674870610920848203139983388374992499997791
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/140.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 140.csrng_err.1215790175
coverage files:
model(design data) : /workspace/coverage/default/140.csrng_err.1215790175/icc_57048ec4_251369e9.ucm
data : /workspace/coverage/default/140.csrng_err.1215790175/icc_57048ec4_251369e9.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Jun 11, 2024 at 13:45:29 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1
258.csrng_err.5563229322481415659345928457590019032544713624284482015039176819674633321299
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/258.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 258.csrng_err.3043867475
coverage files:
model(design data) : /workspace/coverage/default/258.csrng_err.3043867475/icc_57048ec4_251369e9.ucm
data : /workspace/coverage/default/258.csrng_err.3043867475/icc_57048ec4_251369e9.ucd
TOOL: xrun(64) 21.09-s006: Exiting on Jun 11, 2024 at 13:46:29 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1
... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
0.csrng_stress_all.1225466984978947167069878549836405026927296422553824031975900387455411980563
Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
UVM_ERROR @ 27421713892 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 27421713892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
26.csrng_cmds.43142115736328218143583941215389551512217651696649467974968377133421976825125
Line 376, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_cmds/latest/run.log
UVM_FATAL @ 7704156571 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (85431684007746917907843081939239964728 [0x40458b394b64cb3a9faa7101955e1038] vs 0 [0x0])
UVM_INFO @ 7704156571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
46.csrng_cmds.20357845944132740446637908361243057078833510887489880975036998045102534163037
Line 386, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_cmds/latest/run.log
UVM_FATAL @ 57275345035 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
UVM_INFO @ 57275345035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1766): Assertion CsrngUniZeroizeKey_A has failed has 1 failures:
163.csrng_intr.114035718751090555092984279345919815964389215184657382743618199035538569751639
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/163.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1766): (time 52992228 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 52992228 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 52992228 ps: (csrng_core.sv:1766) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 52992228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---