CSRNG Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	46.134us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	63.027us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	63.290us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	45.000s	2.014ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	822.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	34.598us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	63.290us	20	20	100.00
		csrng_csr_aliasing	12.000s	822.179us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	52.037us	198	200	99.00
V2	alerts	csrng_alert	53.000s	2.718ms	500	500	100.00
V2	err	csrng_err	19.000s	24.818us	496	500	99.20
V2	cmds	csrng_cmds	10.233m	40.203ms	49	50	98.00
V2	life cycle	csrng_cmds	10.233m	40.203ms	49	50	98.00
V2	stress_all	csrng_stress_all	20.467m	46.602ms	49	50	98.00
V2	intr_test	csrng_intr_test	13.000s	14.714us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	15.078us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	508.662us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	508.662us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	63.027us	5	5	100.00
		csrng_csr_rw	5.000s	63.290us	20	20	100.00
		csrng_csr_aliasing	12.000s	822.179us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	438.593us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	63.027us	5	5	100.00
		csrng_csr_rw	5.000s	63.290us	20	20	100.00
		csrng_csr_aliasing	12.000s	822.179us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	438.593us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	6.000s	249.035us	5	5	100.00
		csrng_tl_intg_err	15.000s	854.073us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	26.464us	50	50	100.00
		csrng_csr_rw	5.000s	63.290us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	2.718ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.467m	46.602ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	2.718ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.467m	46.602ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	2.718ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	854.073us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
		csrng_sec_cm	6.000s	249.035us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	52.037us	198	200	99.00
		csrng_err	19.000s	24.818us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	19.850m	39.969ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	98.23	95.85	98.86	96.38	91.90	100.00	97.32	90.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.32018674720732018994662025854084484345449176942515737701134437786071040418378
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4250750223 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4250750223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.45025501243632241775127603018008728670007767007088995215085917949269788525755
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3414921207 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3414921207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

121.csrng_err.86409048648991054406410235099835795267801650781354465870785808527947159044739
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/121.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  121.csrng_err.3083338371
  
  coverage files:
    model(design data) :  /workspace/coverage/default/121.csrng_err.3083338371/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/121.csrng_err.3083338371/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 23, 2024 at 16:39:23 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

140.csrng_err.89471701691236336189515910495442948051228046957307089463590578964674033441234
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/140.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  140.csrng_err.2451266002
  
  coverage files:
    model(design data) :  /workspace/coverage/default/140.csrng_err.2451266002/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/140.csrng_err.2451266002/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 23, 2024 at 16:40:00 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 2.csrng_stress_all_with_rand_reset.74328822455743259405318521507801682547366543590666283417078186048432835952666
    Line 397, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18506949646 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18506949646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.88966989203793165705039922509875933433611628304648144225961501271628380715036
    Line 400, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39969232262 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39969232262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

41.csrng_intr.58653755861548020569423042084419630220504078195915318613628262123026820136473
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 25261437 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 25261437 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  25261437 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  25261437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

87.csrng_intr.31306205605503938226479388501547557431793517573301681127394195060020628778201
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 43745023 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 43745023 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  43745023 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  43745023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 12.csrng_cmds.8246178387924211105407435671388986562330968381592502362585810354238935085127
    Line 376, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 669706005 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 669706005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 42.csrng_stress_all.99298073948973824392585012362631720611944770833279392997953448962387402390141
    Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  39655187 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  39655187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```