CSRNG Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	53.663us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	54.826us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	20.937us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	522.822us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	791.008us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	128.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	20.937us	20	20	100.00
		csrng_csr_aliasing	12.000s	791.008us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	17.000s	36.033us	197	200	98.50
V2	alerts	csrng_alert	1.033m	3.995ms	500	500	100.00
V2	err	csrng_err	18.000s	20.324us	490	500	98.00
V2	cmds	csrng_cmds	8.283m	41.560ms	50	50	100.00
V2	life cycle	csrng_cmds	8.283m	41.560ms	50	50	100.00
V2	stress_all	csrng_stress_all	24.150m	22.650ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	123.338us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	40.894us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	966.250us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	966.250us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	54.826us	5	5	100.00
		csrng_csr_rw	8.000s	20.937us	20	20	100.00
		csrng_csr_aliasing	12.000s	791.008us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	185.121us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	54.826us	5	5	100.00
		csrng_csr_rw	8.000s	20.937us	20	20	100.00
		csrng_csr_aliasing	12.000s	791.008us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	185.121us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	6.000s	188.090us	5	5	100.00
		csrng_tl_intg_err	13.000s	792.581us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	14.000s	91.378us	50	50	100.00
		csrng_csr_rw	8.000s	20.937us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.033m	3.995ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.150m	22.650ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.033m	3.995ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.150m	22.650ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.033m	3.995ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	792.581us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
		csrng_sec_cm	6.000s	188.090us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	17.000s	36.033us	197	200	98.50
		csrng_err	18.000s	20.324us	490	500	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	26.050m	88.708ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1605	1670	96.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.04	93.49	85.21	95.38	81.22	91.90	100.00	97.58	90.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test csrng_stress_all_with_rand_reset has 33 failures.
  - 1.csrng_stress_all_with_rand_reset.85684683169354104035502987360401147407551510343811462295168434536008864577683
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2978356408 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2978356408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.31968399122353537578430401522630346184807781337904994441508019562045482846277
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3212217094 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3212217094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test csrng_stress_all_with_rand_reset has 17 failures.
  - 0.csrng_stress_all_with_rand_reset.50738606994214097590922839163219639659994930391538486636822203240812173640464
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2509822829 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2509822829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.27600112458500101674553229469740520237916727092131189075592829191944729522657
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 643152188 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 643152188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

88.csrng_err.59140599205658558817034607185318649817112444440096329456502549150379269535290
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/88.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 8183931 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   8183931 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   8183931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

122.csrng_err.115513785484530891260582582329124090546734769506730516999341480065634542339708
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/122.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2437628 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2437628 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2437628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

24.csrng_intr.76953231863466051097870901945838223172054078228158454827482422030347979446817
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 11091708 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 11091708 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  11091708 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  11091708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.csrng_intr.81519778765506140701376464666143817650399517114253074606190593388336334735888
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 12981476 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 12981476 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  12981476 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  12981476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 2 failures:

Test csrng_err has 2 failures.

126.csrng_err.93569324616036401470466069253853604922501620049690695348236006072456559337409
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/126.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 25332406 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 25332406 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 25332406 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  25332406 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  25332406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

128.csrng_err.113215334462514241521678960937465022256659377578767941707955504631401572534897
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/128.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 33726119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 33726119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 33726119 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  33726119 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  33726119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 19.csrng_stress_all.67705726094146786326858441341152173000802335790840173686702301193904163963212
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1339988823 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1339988823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 27.csrng_stress_all.39455411091585066182272631108952721470511850962463059236496859371856777014943
    Line 328, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5128574196 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5128574196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 44.csrng_err.41624034762828597982148632065545793698739180202596628504340169207359293884505
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_err/latest/run.log
```
  UVM_ERROR @  13637740 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  13637740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

173.csrng_err.16603169882505654359285712214792272693571885302027183977343192824433797930376
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/173.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  173.csrng_err.4280720776
  
  coverage files:
    model(design data) :  /workspace/coverage/default/173.csrng_err.4280720776/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/173.csrng_err.4280720776/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 13, 2024 at 12:30:23 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1