CSRNG Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	75.381us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	20.505us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	205.516us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	58.000s	3.466ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	767.304us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	376.189us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	205.516us	20	20	100.00
		csrng_csr_aliasing	12.000s	767.304us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	173.322us	198	200	99.00
V2	alerts	csrng_alert	52.000s	3.583ms	500	500	100.00
V2	err	csrng_err	14.000s	20.532us	493	500	98.60
V2	cmds	csrng_cmds	9.683m	32.727ms	49	50	98.00
V2	life cycle	csrng_cmds	9.683m	32.727ms	49	50	98.00
V2	stress_all	csrng_stress_all	34.033m	124.873ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	12.198us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	44.983us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.482ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.482ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	20.505us	5	5	100.00
		csrng_csr_rw	5.000s	205.516us	20	20	100.00
		csrng_csr_aliasing	12.000s	767.304us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	567.770us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	20.505us	5	5	100.00
		csrng_csr_rw	5.000s	205.516us	20	20	100.00
		csrng_csr_aliasing	12.000s	767.304us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	567.770us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	6.000s	135.803us	5	5	100.00
		csrng_tl_intg_err	13.000s	472.207us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	22.557us	50	50	100.00
		csrng_csr_rw	5.000s	205.516us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	52.000s	3.583ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	34.033m	124.873ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	52.000s	3.583ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	34.033m	124.873ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	52.000s	3.583ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	472.207us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
		csrng_sec_cm	6.000s	135.803us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	173.322us	198	200	99.00
		csrng_err	14.000s	20.532us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	46.500m	106.237ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1608	1630	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.63555261710122148776103467948391489537996210926288551259639835839497962368424
    Line 295, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1097316691 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1097316691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.93159566235022022009794101979860767494869063780001636857543960607733442789466
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11809361164 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11809361164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:

Test csrng_err has 7 failures.

69.csrng_err.36505004589344476238530398037411839023241011326207943368552516550396845309404
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/69.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  69.csrng_err.2100116956
  
  coverage files:
    model(design data) :  /workspace/coverage/default/69.csrng_err.2100116956/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/69.csrng_err.2100116956/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 21, 2024 at 16:39:58 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

137.csrng_err.70758468316886781348211794939966244690350209189586090156756696635529400283612
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/137.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  137.csrng_err.2594304476
  
  coverage files:
    model(design data) :  /workspace/coverage/default/137.csrng_err.2594304476/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/137.csrng_err.2594304476/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 21, 2024 at 16:40:39 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 4.csrng_stress_all_with_rand_reset.10898312627453766294019710521561838086331028957744550259614168829436202374447
    Line 507, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106236536498 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106236536498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.29686843341572006359304095885244087179612280267948701812719006509249196889216
    Line 343, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13621564860 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13621564860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

9.csrng_intr.69516268081904958225410981562357471411220311118756423499464628558770586409600
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 44640193 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 44640193 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  44640193 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  44640193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.csrng_intr.89129490683394078008326586688968830704449675361766056854674036052885746530713
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 264650903 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 264650903 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 264650903 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 264650903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 31.csrng_stress_all.95314994167871701889774183937165487661010745370669513349871748144187294083585
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 195840496 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 195840496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.csrng_stress_all.91783620603154759499617325697870780210022929820685688566959032400902912110926
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 257410823 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 257410823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 3.csrng_cmds.101779945179149455666928784846578991854437419567496923550013096173281838785896
    Line 406, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 4330529589 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (41261953560076618289334698998696607683 [0x1f0ac36095dec2143f362b043e217fc3] vs 0 [0x0])
  UVM_INFO @ 4330529589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```