CSRNG Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	135.060us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	51.021us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	225.606us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	526.050us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	121.585us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	305.102us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	225.606us	20	20	100.00
		csrng_csr_aliasing	7.000s	121.585us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	198.037us	198	200	99.00
V2	alerts	csrng_alert	1.583m	8.153ms	500	500	100.00
V2	err	csrng_err	8.000s	31.917us	497	500	99.40
V2	cmds	csrng_cmds	7.283m	31.234ms	49	50	98.00
V2	life cycle	csrng_cmds	7.283m	31.234ms	49	50	98.00
V2	stress_all	csrng_stress_all	45.300m	209.931ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	38.118us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	96.260us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	539.167us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	539.167us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	51.021us	5	5	100.00
		csrng_csr_rw	5.000s	225.606us	20	20	100.00
		csrng_csr_aliasing	7.000s	121.585us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	143.660us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	51.021us	5	5	100.00
		csrng_csr_rw	5.000s	225.606us	20	20	100.00
		csrng_csr_aliasing	7.000s	121.585us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	143.660us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	12.000s	580.423us	5	5	100.00
		csrng_tl_intg_err	12.000s	339.369us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	13.836us	50	50	100.00
		csrng_csr_rw	5.000s	225.606us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.583m	8.153ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	45.300m	209.931ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.583m	8.153ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	45.300m	209.931ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.583m	8.153ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	339.369us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
		csrng_sec_cm	12.000s	580.423us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	198.037us	198	200	99.00
		csrng_err	8.000s	31.917us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	31.533m	115.821ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	98.21	95.79	98.84	96.38	91.77	100.00	97.14	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.104213510574805670164075560059827066363676183240320218089523434782298907147993
    Line 343, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15532936838 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15532936838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.110818694847712183275212191031963643895539919680746805491230469007095409506817
    Line 398, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115820881560 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 115820881560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 3.csrng_stress_all_with_rand_reset.51530172011749802250636115279534133359411967670427861187441973536659715069177
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17836735493 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17836735493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.45678170809818010264747834068197739626184580036231330118329885643205270031168
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25266831961 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25266831961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 8.csrng_stress_all.35224579591666513775416074399931577649302132112216313998622433634829893756997
    Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 166727991 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 166727991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.csrng_stress_all.90383908906413865152691809171542389261990333000526419136566259333602384138766
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3253818420 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3253818420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

116.csrng_intr.102096367597566238491649605095117516449720306798395682725070271282948831872807
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 88052407 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 88052407 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  88052407 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  88052407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

120.csrng_intr.32587430289390965777918107544363244773076957509906408336425935810305215080222
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/120.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 92754657 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 92754657 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  92754657 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  92754657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

256.csrng_err.65824738301221951025893215149906468622308770012230494784999325232497024562369
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/256.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  256.csrng_err.3184260289
  
  coverage files:
    model(design data) :  /workspace/coverage/default/256.csrng_err.3184260289/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/256.csrng_err.3184260289/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 02, 2024 at 09:21:26 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

323.csrng_err.100067185718455523711619551878135310229419533187775767478131650415031280676402
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/323.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  323.csrng_err.771436082
  
  coverage files:
    model(design data) :  /workspace/coverage/default/323.csrng_err.771436082/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/323.csrng_err.771436082/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 02, 2024 at 09:21:49 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 2.csrng_stress_all.19966058785623833538230470792254741871330913255691226553216900745720282827610
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  19944478 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  19944478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 8.csrng_err.58301057662842673829082479957360867671927441857105082062753500491255856195327
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_err/latest/run.log
```
  UVM_ERROR @   8660472 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   8660472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 21.csrng_cmds.55148236016870784178432449878225009929129429784000553503984847226640521499175
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 4146674652 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (152030528886439949520330904648495679967 [0x726003ca37a62a74d1a2f58e9d5c49df] vs 0 [0x0])
  UVM_INFO @ 4146674652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```