CSRNG Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	85.726us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	184.174us	5	5	100.00
V1	csr_rw	csrng_csr_rw	9.000s	25.415us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	43.000s	2.485ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	338.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	19.000s	18.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	9.000s	25.415us	20	20	100.00
		csrng_csr_aliasing	11.000s	338.477us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	380.858us	197	200	98.50
V2	alerts	csrng_alert	1.333m	6.089ms	500	500	100.00
V2	err	csrng_err	5.000s	20.272us	498	500	99.60
V2	cmds	csrng_cmds	5.317m	6.607ms	48	50	96.00
V2	life cycle	csrng_cmds	5.317m	6.607ms	48	50	96.00
V2	stress_all	csrng_stress_all	1.323h	360.838ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	51.377us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	192.498us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.309ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.309ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	184.174us	5	5	100.00
		csrng_csr_rw	9.000s	25.415us	20	20	100.00
		csrng_csr_aliasing	11.000s	338.477us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	881.045us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	184.174us	5	5	100.00
		csrng_csr_rw	9.000s	25.415us	20	20	100.00
		csrng_csr_aliasing	11.000s	338.477us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	881.045us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	7.000s	438.301us	5	5	100.00
		csrng_tl_intg_err	13.000s	160.366us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	133.045us	50	50	100.00
		csrng_csr_rw	9.000s	25.415us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.333m	6.089ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.323h	360.838ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.333m	6.089ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.323h	360.838ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.333m	6.089ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	160.366us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
		csrng_sec_cm	7.000s	438.301us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	380.858us	197	200	98.50
		csrng_err	5.000s	20.272us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.025h	145.303ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	98.23	95.85	98.84	96.43	91.90	100.00	97.32	90.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.37101948431156535169157911714701073866152543594334536085438069218722661169722
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26769218933 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26769218933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.105207030952366313503943270244107190948907915144525001406060137671986233846741
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6407772557 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6407772557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 2.csrng_stress_all_with_rand_reset.82851954412241591356296057244700003595393362393483353007808510479450783935055
    Line 367, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7714881680 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7714881680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.8172088408770992568570341471659043920354400224397114301541819013382273663084
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6900732311 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6900732311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

44.csrng_intr.65073085961275420548001537211115804264900025761676848223840006942714609700377
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 145357573 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 145357573 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 145357573 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 145357573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

141.csrng_intr.78188248915360222471539010156590941995983702228904236674224195226182439638641
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/141.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 15341323 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 15341323 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15341323 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15341323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 4.csrng_cmds.59655709735644952157510880162977458177928114168312573568829898112125974280756
    Line 386, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 3440137896 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3440137896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

5.csrng_err.110331304376031064117811674230166324030505476650232617409047349602170547853051
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  5.csrng_err.2519848699
  
  coverage files:
    model(design data) :  /workspace/coverage/default/5.csrng_err.2519848699/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/5.csrng_err.2519848699/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 28, 2024 at 17:06:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 23.csrng_stress_all.41220167496611176382584159310813076472289053039277055541390810697951544574007
    Line 339, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 28172334037 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 28172334037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 30.csrng_cmds.85563356121799940489254637402190904824838204165097495742334210689043372043385
    Line 406, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 1469254041 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (201041147536380718845789740420671828758 [0x973f1dda1d93037eeb56ee9ddcbd7316] vs 0 [0x0])
  UVM_INFO @ 1469254041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 199.csrng_err.108803038374610463009130689622456654165737891385509802680529658376318821187202
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/199.csrng_err/latest/run.log
```
  UVM_ERROR @  11339020 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11339020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```