CSRNG Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	363.043us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	16.066us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	17.265us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	41.000s	1.884ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	143.473us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	56.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	17.265us	20	20	100.00
		csrng_csr_aliasing	8.000s	143.473us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	384.043us	193	200	96.50
V2	alerts	csrng_alert	1.550m	7.501ms	500	500	100.00
V2	err	csrng_err	5.000s	20.458us	496	500	99.20
V2	cmds	csrng_cmds	14.533m	74.796ms	48	50	96.00
V2	life cycle	csrng_cmds	14.533m	74.796ms	48	50	96.00
V2	stress_all	csrng_stress_all	32.317m	136.345ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	17.851us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	182.252us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	656.856us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	656.856us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	16.066us	5	5	100.00
		csrng_csr_rw	8.000s	17.265us	20	20	100.00
		csrng_csr_aliasing	8.000s	143.473us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	164.081us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	16.066us	5	5	100.00
		csrng_csr_rw	8.000s	17.265us	20	20	100.00
		csrng_csr_aliasing	8.000s	143.473us	5	5	100.00
		csrng_same_csr_outstanding	15.000s	164.081us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	6.000s	121.140us	5	5	100.00
		csrng_tl_intg_err	27.000s	527.221us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	15.111us	50	50	100.00
		csrng_csr_rw	8.000s	17.265us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.550m	7.501ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.317m	136.345ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.550m	7.501ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.317m	136.345ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.550m	7.501ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	27.000s	527.221us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
		csrng_sec_cm	6.000s	121.140us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	384.043us	193	200	96.50
		csrng_err	5.000s	20.458us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	48.383m	173.498ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1605	1630	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 1.csrng_stress_all_with_rand_reset.73391658407537055688714024742109848859907117402530805017202540977666330294446
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 961867823 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 961867823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.90237617104216975577875534001967457441013970179228606678721531420073849212178
    Line 407, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173497941764 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 173497941764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 7 failures:

Test csrng_intr has 7 failures.

43.csrng_intr.3982562167270263924416703146809399631906015709917596424144531437802334391480
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 13885408 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 13885408 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  13885408 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  13885408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

60.csrng_intr.15363861873089285259538192558527909902062944468068237552123008759549722240458
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/60.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 62852973 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 62852973 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  62852973 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  62852973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

77.csrng_err.110882976235165920596322435750919748247751772793106376193825458589687619282186
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/77.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  77.csrng_err.874013962
  
  coverage files:
    model(design data) :  /workspace/coverage/default/77.csrng_err.874013962/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/77.csrng_err.874013962/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 29, 2024 at 18:07:27 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

215.csrng_err.88368342431335120034656052173718932147380511430149415868938762784724315447918
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/215.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  215.csrng_err.114467438
  
  coverage files:
    model(design data) :  /workspace/coverage/default/215.csrng_err.114467438/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/215.csrng_err.114467438/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 29, 2024 at 18:09:42 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.60845507728156404403388352558185622521705341946679493052738475888300637734022
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 368381129 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 368381129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.106940274753000894622426988567386298711737533415736240121995117225290869587667
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3417861725 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3417861725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 4.csrng_cmds.41136868957723066940701073434233948532657548345942579154589474107677660592771
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 7627366262 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (27883070194384284224294439207940326467 [0x14fa157fe6f1dc5496871e708e3b0443] vs 0 [0x0])
  UVM_INFO @ 7627366262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 14.csrng_stress_all.71092825268184554674314404227177000536315383055502121045550420478240772492843
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  52042087 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  52042087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 15.csrng_cmds.36417215427630645350128012939106878375631818874342392975274417201382782866425
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 18727497678 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 18727497678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 41.csrng_stress_all.63361291262057032950282314118997891545239920162287885335076318179440254797113
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 38213978565 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 38213978565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```