CSRNG Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	91.208us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	104.314us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	106.946us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	524.557us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	345.021us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	406.837us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	106.946us	20	20	100.00
		csrng_csr_aliasing	7.000s	345.021us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	13.753us	196	200	98.00
V2	alerts	csrng_alert	48.000s	2.230ms	500	500	100.00
V2	err	csrng_err	25.000s	33.562us	498	500	99.60
V2	cmds	csrng_cmds	6.867m	10.448ms	49	50	98.00
V2	life cycle	csrng_cmds	6.867m	10.448ms	49	50	98.00
V2	stress_all	csrng_stress_all	45.900m	105.540ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	76.888us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	80.465us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	394.888us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	394.888us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	104.314us	5	5	100.00
		csrng_csr_rw	4.000s	106.946us	20	20	100.00
		csrng_csr_aliasing	7.000s	345.021us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	83.858us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	104.314us	5	5	100.00
		csrng_csr_rw	4.000s	106.946us	20	20	100.00
		csrng_csr_aliasing	7.000s	345.021us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	83.858us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	11.000s	81.857us	5	5	100.00
		csrng_tl_intg_err	13.000s	618.088us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	14.000s	13.319us	50	50	100.00
		csrng_csr_rw	4.000s	106.946us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	48.000s	2.230ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	45.900m	105.540ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	48.000s	2.230ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	45.900m	105.540ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	48.000s	2.230ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	618.088us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
		csrng_sec_cm	11.000s	81.857us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	13.753us	196	200	98.00
		csrng_err	25.000s	33.562us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	19.250m	75.991ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1610	1630	98.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.08	98.19	95.74	98.79	96.38	91.84	100.00	97.14	90.39

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.77950076793251158339096929170044036417535280140813623649706037869438177573795
    Line 304, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3064847875 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3064847875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.55679949391860863630261102096774557146352635157992907363938155876315141274804
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9032649115 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9032649115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 1.csrng_stress_all_with_rand_reset.50162903640507660775792538094492038514397477597159530472114874197242787391930
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5798166748 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5798166748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.73930760061701986580337748115118935790760887475295620687084942938405766405597
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5511009125 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5511009125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

47.csrng_intr.104581569548836600767511506864950451656183719172389326992546744845650635471964
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 17863894 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 17863894 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  17863894 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  17863894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

69.csrng_intr.16008063617882877599714937926736266480396231531245285769249174077959128408460
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/69.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 13752548 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 13752548 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  13752548 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  13752548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 5.csrng_stress_all.68865812193024318338840395391415565242095804159942479105541620985795671409402
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 18342985942 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 18342985942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.csrng_stress_all.113282417464866175279748998563112764701375988717825294987953489497805276620416
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 176376669 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 176376669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 6.csrng_stress_all.71009558003035051846201469181025749840773995989512731965406889666495730460360
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  66818513 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  66818513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 48.csrng_cmds.52370554254879919222321631559459799842288610706883594253043468401634224690420
    Line 386, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/48.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 27942552476 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (261076757391179961289004229747802527727 [0xc4698df2af326f961b237aacc0c657ef] vs 0 [0x0])
  UVM_INFO @ 27942552476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

101.csrng_intr.11211960443145166321597358580145855237079824429280284302885177700824450202874
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 48702830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 48702830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 48702830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 48702830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 48702830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

477.csrng_err.62335663937525385391393212548198317130755907820470457252694136556081317408503
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/477.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  477.csrng_err.2523918071
  
  coverage files:
    model(design data) :  /workspace/coverage/default/477.csrng_err.2523918071/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/477.csrng_err.2523918071/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 27, 2024 at 16:31:27 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 495.csrng_err.43511399953802891421121437405007172711819377541998604058842661499199665646959
    Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/495.csrng_err/latest/run.log
```
  UVM_ERROR @  33537242 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  33537242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```