CSRNG Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	52.850us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	51.071us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	124.608us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	51.000s	2.874ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	17.000s	164.998us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	38.125us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	124.608us	20	20	100.00
		csrng_csr_aliasing	17.000s	164.998us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	121.149us	197	200	98.50
V2	alerts	csrng_alert	1.250m	5.999ms	500	500	100.00
V2	err	csrng_err	19.000s	19.861us	495	500	99.00
V2	cmds	csrng_cmds	8.917m	32.289ms	49	50	98.00
V2	life cycle	csrng_cmds	8.917m	32.289ms	49	50	98.00
V2	stress_all	csrng_stress_all	25.383m	120.905ms	46	50	92.00
V2	intr_test	csrng_intr_test	14.000s	27.027us	50	50	100.00
V2	alert_test	csrng_alert_test	27.000s	26.319us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	1.794ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	1.794ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	51.071us	5	5	100.00
		csrng_csr_rw	8.000s	124.608us	20	20	100.00
		csrng_csr_aliasing	17.000s	164.998us	5	5	100.00
		csrng_same_csr_outstanding	16.000s	197.854us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	51.071us	5	5	100.00
		csrng_csr_rw	8.000s	124.608us	20	20	100.00
		csrng_csr_aliasing	17.000s	164.998us	5	5	100.00
		csrng_same_csr_outstanding	16.000s	197.854us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	10.000s	883.393us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.009ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	42.230us	50	50	100.00
		csrng_csr_rw	8.000s	124.608us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.250m	5.999ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.383m	120.905ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.250m	5.999ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.383m	120.905ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.250m	5.999ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.009ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
		csrng_sec_cm	10.000s	883.393us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	121.149us	197	200	98.50
		csrng_err	19.000s	19.861us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	58.850m	142.332ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1607	1630	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	98.28	95.95	98.91	96.48	91.90	100.00	97.32	90.39

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 1.csrng_stress_all_with_rand_reset.38997722483921531431224949458387390840964648428688524404668469293794455382106
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1018990722 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1018990722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.112366970562711476151350608968876144503144664201142658637903406935442058206944
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1899678759 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1899678759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

128.csrng_err.32556853097808173733748250782841956955350195442036702878201049583145576174017
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/128.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  128.csrng_err.1194201537
  
  coverage files:
    model(design data) :  /workspace/coverage/default/128.csrng_err.1194201537/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/128.csrng_err.1194201537/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 30, 2024 at 16:30:18 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

343.csrng_err.39865355045778540433783086135196667231979262968757424996969261509630053309440
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/343.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  343.csrng_err.3970948096
  
  coverage files:
    model(design data) :  /workspace/coverage/default/343.csrng_err.3970948096/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/343.csrng_err.3970948096/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 30, 2024 at 16:30:32 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.97050319072548112234925897182799126510967344423729215195614164749448242499542
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5824691859 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5824691859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.109278695008356079475546055631063205335861531292339945512553035482489372706440
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 995097527 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 995097527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 2.csrng_stress_all.79827638493412344855408079130423530588992596272857752591267774598602839362290
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 265709043 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 265709043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.csrng_stress_all.16705504527806202181392912110972740611406839733087458819983733265844304760472
    Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 649302255 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 649302255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

150.csrng_intr.40526603229411067798452358313701248774873864659192568439261359304385050063846
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/150.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 27942331 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 27942331 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  27942331 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  27942331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

166.csrng_intr.69921050974544781049693486433135980995363191352214638485354024847369793603125
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/166.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 21681595 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 21681595 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21681595 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21681595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 45.csrng_cmds.20151312045021571699360085386927700581571072081756251930803378963995853044424
    Line 376, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 5330126700 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 5330126700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 47.csrng_stress_all.64073674712168706664212325172822335040643153971599497878956775143509162077615
    Line 359, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8263795478 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8263795478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```