CSRNG Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	203.393us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	58.112us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	18.745us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.033m	3.986ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	483.100us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	90.455us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	18.745us	20	20	100.00
		csrng_csr_aliasing	9.000s	483.100us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	59.398us	197	200	98.50
V2	alerts	csrng_alert	59.000s	3.770ms	500	500	100.00
V2	err	csrng_err	14.000s	20.412us	493	500	98.60
V2	cmds	csrng_cmds	7.833m	29.251ms	49	50	98.00
V2	life cycle	csrng_cmds	7.833m	29.251ms	49	50	98.00
V2	stress_all	csrng_stress_all	34.800m	177.748ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	42.759us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	279.795us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	118.334us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	118.334us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	58.112us	5	5	100.00
		csrng_csr_rw	4.000s	18.745us	20	20	100.00
		csrng_csr_aliasing	9.000s	483.100us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	183.603us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	58.112us	5	5	100.00
		csrng_csr_rw	4.000s	18.745us	20	20	100.00
		csrng_csr_aliasing	9.000s	483.100us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	183.603us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	7.000s	191.696us	5	5	100.00
		csrng_tl_intg_err	17.000s	1.268ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	92.028us	50	50	100.00
		csrng_csr_rw	4.000s	18.745us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	59.000s	3.770ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	34.800m	177.748ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	59.000s	3.770ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	34.800m	177.748ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	59.000s	3.770ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	1.268ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
		csrng_sec_cm	7.000s	191.696us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	59.398us	197	200	98.50
		csrng_err	14.000s	20.412us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.382h	69.181ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1607	1630	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.53

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:

Test csrng_err has 7 failures.

102.csrng_err.66797566313883736499321598897242265291211314725308589071586270250414700342657
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/102.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  102.csrng_err.3068505473
  
  coverage files:
    model(design data) :  /workspace/coverage/default/102.csrng_err.3068505473/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/102.csrng_err.3068505473/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 03, 2024 at 17:40:04 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

224.csrng_err.98122769744173090686704889337574868315806703784122149993909373135368958078670
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/224.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  224.csrng_err.1301638862
  
  coverage files:
    model(design data) :  /workspace/coverage/default/224.csrng_err.1301638862/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/224.csrng_err.1301638862/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 03, 2024 at 17:40:54 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.72444631135781573615863528542552524433380218756675895475448161070639961799452
    Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9976739718 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9976739718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.41172741499958830855185268752094462028693468388626224296474360284158417987394
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 285151840 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 285151840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 4.csrng_stress_all_with_rand_reset.6918519928673215898491276731605116259861933701046191789290714158714716728343
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3005348683 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3005348683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.11224104572957329822399974699636004483458042466649178900805795735959550750686
    Line 866, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 69181496129 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 69181496129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

6.csrng_intr.19088899473620216410194239009155890432613137186747958275342045263465911915272
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 21555254 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 21555254 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21555254 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21555254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

71.csrng_intr.69232795409940732963975577906484456454573670315082636172936451850774938028819
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/71.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 55234157 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 55234157 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  55234157 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  55234157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 24.csrng_cmds.25020094057278449291760435903896836858743470762020871796913878118186050364981
    Line 386, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 23021428002 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (248712164696141193962556655102606471745 [0xbb1c38761b5793b738e76dff1eac7241] vs 0 [0x0])
  UVM_INFO @ 23021428002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 28.csrng_stress_all.34741704552541888607153493790355146916170843129379168291334951516957265240477
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4078107663 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4078107663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 35.csrng_stress_all.11550317786613614252027994027258757205944996781706378880838690594215692938153
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 74186549563 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 74186549563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```