CSRNG Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	92.554us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.925us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	106.390us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	1.032ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	302.699us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	145.801us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	106.390us	20	20	100.00
		csrng_csr_aliasing	7.000s	302.699us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	97.163us	198	200	99.00
V2	alerts	csrng_alert	1.283m	6.531ms	500	500	100.00
V2	err	csrng_err	21.000s	24.555us	493	500	98.60
V2	cmds	csrng_cmds	11.367m	68.753ms	50	50	100.00
V2	life cycle	csrng_cmds	11.367m	68.753ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.017m	184.623ms	45	50	90.00
V2	intr_test	csrng_intr_test	4.000s	84.235us	50	50	100.00
V2	alert_test	csrng_alert_test	18.000s	28.651us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	1.046ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	1.046ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.925us	5	5	100.00
		csrng_csr_rw	5.000s	106.390us	20	20	100.00
		csrng_csr_aliasing	7.000s	302.699us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	372.679us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.925us	5	5	100.00
		csrng_csr_rw	5.000s	106.390us	20	20	100.00
		csrng_csr_aliasing	7.000s	302.699us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	372.679us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	15.000s	117.791us	5	5	100.00
		csrng_tl_intg_err	23.000s	2.019ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	15.000s	24.723us	50	50	100.00
		csrng_csr_rw	5.000s	106.390us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.283m	6.531ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.017m	184.623ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.283m	6.531ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.017m	184.623ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.283m	6.531ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	2.019ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
		csrng_sec_cm	15.000s	117.791us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	97.163us	198	200	99.00
		csrng_err	21.000s	24.555us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.119h	107.598ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1606	1630	98.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.52127515280429988680459146545190001222038206370462113290483292104799274692328
    Line 502, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27206351513 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27206351513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.4721561976513700955836653147451854944439750533811094622121583130799688184179
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 484527906 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 484527906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:

Test csrng_err has 7 failures.

127.csrng_err.46643324912193442275966075470005134283706258311093907961256643614041176740844
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/127.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  127.csrng_err.107680748
  
  coverage files:
    model(design data) :  /workspace/coverage/default/127.csrng_err.107680748/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/127.csrng_err.107680748/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 04, 2024 at 16:37:47 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

128.csrng_err.105396430567680200807051519575026462554781787294133927665381018790890895171980
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/128.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  128.csrng_err.2907038092
  
  coverage files:
    model(design data) :  /workspace/coverage/default/128.csrng_err.2907038092/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/128.csrng_err.2907038092/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 04, 2024 at 16:37:49 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 23.csrng_stress_all.71740603405929066304395736182754191481267204789445205521185443501347603808379
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 39558527028 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 39558527028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all.89929878131226400838299800775076541085390195317806289306129888343568451436454
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1676782628 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1676782628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 1.csrng_stress_all_with_rand_reset.95023364114563122737520179460164798244857037739255497045493375419805767590980
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13445592120 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13445592120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.8919016741797728518920709212098272436655516328519133450154226843217227663893
    Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5439568680 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5439568680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

120.csrng_intr.61920686218822910062841073977701973276737416668024743322337124854063820016710
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/120.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 266726656 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 266726656 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 266726656 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 266726656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

166.csrng_intr.34139422712194492182760103289085341594190796377990678942021413268300132311761
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/166.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 21772025 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 21772025 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 21772025 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 21772025 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  21772025 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 11.csrng_stress_all.79362431121008224174828233600408420437723781904917597796152007965137405921427
    Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5526696397 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5526696397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```