CSRNG Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	11.000s	364.625us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	79.394us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	23.195us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	50.000s	2.344ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	460.985us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	379.520us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	23.195us	20	20	100.00
		csrng_csr_aliasing	9.000s	460.985us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	71.149us	198	200	99.00
V2	alerts	csrng_alert	50.000s	3.315ms	500	500	100.00
V2	err	csrng_err	19.000s	19.090us	494	500	98.80
V2	cmds	csrng_cmds	8.533m	44.357ms	50	50	100.00
V2	life cycle	csrng_cmds	8.533m	44.357ms	50	50	100.00
V2	stress_all	csrng_stress_all	46.317m	191.586ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	151.350us	50	50	100.00
V2	alert_test	csrng_alert_test	20.000s	17.617us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.467ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.467ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	79.394us	5	5	100.00
		csrng_csr_rw	4.000s	23.195us	20	20	100.00
		csrng_csr_aliasing	9.000s	460.985us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	378.853us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	79.394us	5	5	100.00
		csrng_csr_rw	4.000s	23.195us	20	20	100.00
		csrng_csr_aliasing	9.000s	460.985us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	378.853us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	10.000s	109.393us	5	5	100.00
		csrng_tl_intg_err	13.000s	629.929us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	39.858us	50	50	100.00
		csrng_csr_rw	4.000s	23.195us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	50.000s	3.315ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	46.317m	191.586ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	50.000s	3.315ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	46.317m	191.586ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	50.000s	3.315ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	629.929us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
		csrng_sec_cm	10.000s	109.393us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	71.149us	198	200	99.00
		csrng_err	19.000s	19.090us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	16.067m	43.868ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1610	1630	98.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	98.23	95.85	98.84	96.43	91.90	100.00	97.32	90.53

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.84662990104725503924174757113080593199961670320207765747480976485926358809275
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 225564274 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 225564274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.73303522935006720620530150960605212210737635040951942246933083596497372061811
    Line 301, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2884842053 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2884842053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:

Test csrng_err has 6 failures.

18.csrng_err.315785343156889440867603310767371401225133877171740552557813286159411156616
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  18.csrng_err.3523581576
  
  coverage files:
    model(design data) :  /workspace/coverage/default/18.csrng_err.3523581576/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/18.csrng_err.3523581576/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 06, 2024 at 16:27:15 PDT  (total: 00:00:08)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

88.csrng_err.87691443533893377932566336900898027757840865652236489014650229331418300209637
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/88.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  88.csrng_err.1430706661
  
  coverage files:
    model(design data) :  /workspace/coverage/default/88.csrng_err.1430706661/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/88.csrng_err.1430706661/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 06, 2024 at 16:28:03 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 4.csrng_stress_all_with_rand_reset.50658741412437847126215652907008782362584653808570947172454976343391740571445
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1883339292 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1883339292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.84011954708924764212150096991380018254873263496825391505934474568975606726123
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20656689853 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20656689853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 38.csrng_stress_all.50004953541805533300081608362465464186480153689702181387028160142809585079491
    Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1641811836 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1641811836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.csrng_stress_all.113560820161890482920220004679474726860583348349852836745880617256689273468264
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7368490906 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7368490906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

106.csrng_intr.35749089254175214676592096367256859581252267459655459143593163326420269852292
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/106.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 13936924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 13936924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 13936924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 13936924 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  13936924 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

126.csrng_intr.28951866782366473470585437970189633587495923851436897302851548703995661329716
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/126.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 16311055 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 16311055 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  16311055 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  16311055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---