CSRNG Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	402.305us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	32.000s	36.846us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.300m	22.228us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	56.000s	1.400ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	34.000s	107.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.150m	180.086us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.300m	22.228us	20	20	100.00
		csrng_csr_aliasing	34.000s	107.010us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.450m	111.908us	199	200	99.50
V2	alerts	csrng_alert	2.233m	1.982ms	500	500	100.00
V2	err	csrng_err	2.483m	24.400us	499	500	99.80
V2	cmds	csrng_cmds	8.467m	24.490ms	50	50	100.00
V2	life cycle	csrng_cmds	8.467m	24.490ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.083m	104.039ms	49	50	98.00
V2	intr_test	csrng_intr_test	1.233m	72.692us	50	50	100.00
V2	alert_test	csrng_alert_test	12.000s	17.272us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	1.267m	345.051us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	1.267m	345.051us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	32.000s	36.846us	5	5	100.00
		csrng_csr_rw	1.300m	22.228us	20	20	100.00
		csrng_csr_aliasing	34.000s	107.010us	5	5	100.00
		csrng_same_csr_outstanding	1.150m	50.678us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	32.000s	36.846us	5	5	100.00
		csrng_csr_rw	1.300m	22.228us	20	20	100.00
		csrng_csr_aliasing	34.000s	107.010us	5	5	100.00
		csrng_same_csr_outstanding	1.150m	50.678us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	14.000s	425.250us	5	5	100.00
		csrng_tl_intg_err	1.450m	731.594us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	15.890us	50	50	100.00
		csrng_csr_rw	1.300m	22.228us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.233m	1.982ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.083m	104.039ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.233m	1.982ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.083m	104.039ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.233m	1.982ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.450m	731.594us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
		csrng_sec_cm	14.000s	425.250us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.450m	111.908us	199	200	99.50
		csrng_err	2.483m	24.400us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.583m	4.477ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	98.35	96.11	99.07	96.70	91.77	100.00	97.14	90.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.94281470760164981414674919123177707201934946324177611782722206122038723757341
    Line 103, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 225575851 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 225575851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.52964318784645461242063419696344598892171705879563985277272126876362274883463
    Line 97, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105307571 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105307571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 12.csrng_stress_all.46609592166837671012365335222026475551480280952240654349326019646657880033726
    Line 140, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 725194026 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 725194026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_*_*_*_*_*_*_RC0/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

60.csrng_intr.100737402653193797887616360048631708578747369576343196209897245445867494048878
Line 127, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/60.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 85721060 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  85721060 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  85721060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 474.csrng_err.95005464117032820749384354867412904973867315940858807305966251079405174421891
    Line 127, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/csrng-sim-xcelium/474.csrng_err/latest/run.log
```
  UVM_ERROR @   2994572 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   2994572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```