CSRNG Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	15.000s	101.421us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	54.229us	5	5	100.00
V1	csr_rw	csrng_csr_rw	13.000s	17.033us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	37.000s	1.301ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	30.581us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	40.042us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	13.000s	17.033us	20	20	100.00
		csrng_csr_aliasing	9.000s	30.581us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	807.076us	200	200	100.00
V2	alerts	csrng_alert	1.467m	7.051ms	500	500	100.00
V2	err	csrng_err	18.000s	100.448us	500	500	100.00
V2	cmds	csrng_cmds	19.100m	107.138ms	50	50	100.00
V2	life cycle	csrng_cmds	19.100m	107.138ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.950m	88.477ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	12.384us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	243.037us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	644.234us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	644.234us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	54.229us	5	5	100.00
		csrng_csr_rw	13.000s	17.033us	20	20	100.00
		csrng_csr_aliasing	9.000s	30.581us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	56.801us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	54.229us	5	5	100.00
		csrng_csr_rw	13.000s	17.033us	20	20	100.00
		csrng_csr_aliasing	9.000s	30.581us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	56.801us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	10.000s	983.388us	5	5	100.00
		csrng_tl_intg_err	19.000s	1.702ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	15.564us	50	50	100.00
		csrng_csr_rw	13.000s	17.033us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.467m	7.051ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.950m	88.477ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.467m	7.051ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.950m	88.477ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.467m	7.051ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	1.702ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
		csrng_sec_cm	10.000s	983.388us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	807.076us	200	200	100.00
		csrng_err	18.000s	100.448us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.050m	10.172ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.37	98.39	96.21	99.12	96.76	91.90	100.00	97.32	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.15301670730660394634459410106769244759653314056482160303982088241404963278203
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 883584801 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 883584801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.93232778631237675072342932393178540984857934845786438006909487903601102075589
    Line 312, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10171859523 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10171859523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.104568326877485133363501787637480659297838072553354593021946534883929046859490
    Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 651019528 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 651019528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.58630746241167157572629093036747852521779003633600193213533983706017636109871
    Line 287, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5067270981 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5067270981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 11.csrng_stress_all.18249048108865603733858958630447352732436905875120354511760044605375378381391
    Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10377936475 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10377936475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 40.csrng_stress_all.77297796424664394531465318216232382932625531727953451111980465441058048978290
    Line 347, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 209516269 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 209516269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

CSRNG Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`