CSRNG Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	288.150us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	38.238us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	315.116us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	1.728ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	81.971us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	30.860us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	315.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	81.971us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	1.725ms	200	200	100.00
V2	alerts	csrng_alert	1.000m	4.240ms	500	500	100.00
V2	err	csrng_err	14.000s	70.560us	500	500	100.00
V2	cmds	csrng_cmds	10.650m	40.889ms	50	50	100.00
V2	life cycle	csrng_cmds	10.650m	40.889ms	50	50	100.00
V2	stress_all	csrng_stress_all	44.067m	220.478ms	47	50	94.00
V2	intr_test	csrng_intr_test	5.000s	137.229us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	70.358us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	231.147us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	231.147us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	38.238us	5	5	100.00
		csrng_csr_rw	6.000s	315.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	81.971us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	116.490us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	38.238us	5	5	100.00
		csrng_csr_rw	6.000s	315.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	81.971us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	116.490us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	7.000s	449.035us	5	5	100.00
		csrng_tl_intg_err	21.000s	1.609ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	45.059us	50	50	100.00
		csrng_csr_rw	6.000s	315.116us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.000m	4.240ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	44.067m	220.478ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.000m	4.240ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	44.067m	220.478ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.000m	4.240ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	21.000s	1.609ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
		csrng_sec_cm	7.000s	449.035us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	1.725ms	200	200	100.00
		csrng_err	14.000s	70.560us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.000m	951.945us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	98.35	96.11	99.04	96.70	91.90	100.00	97.32	90.65

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:

  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 0.csrng_stress_all_with_rand_reset.1396519008325746884275427570098998880950444211960440809844136131557800239487
      Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 225159804 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 225159804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.15262403781336257692186943403765709457677158545430728606372380292446720487943
      Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 951945060 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 951945060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

  • Test csrng_stress_all has 2 failures.

    • 18.csrng_stress_all.79724727382232782639714036931499741473847308417069917944696756434022208396371
      Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log

        UVM_ERROR @  17103692 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  17103692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.csrng_stress_all.38416045230897995507757225402550918751436239422217560472008789031221276974089
      Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log

        UVM_ERROR @ 70709360826 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 70709360826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 6.csrng_stress_all_with_rand_reset.89318663571568723351031003457715178348968031278556214819176404325396044796685
      Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 990247256 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 990247256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 47.csrng_stress_all.88747007061623852535974718959732126131686399285088293759793415941174865295245
      Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log

        UVM_ERROR @ 15704941291 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 15704941291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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