CSRNG Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	117.782us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.745us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	18.082us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	1.410ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	44.630us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	40.341us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	18.082us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.630us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	1.239ms	200	200	100.00
V2	alerts	csrng_alert	1.167m	5.770ms	500	500	100.00
V2	err	csrng_err	17.000s	25.739us	499	500	99.80
V2	cmds	csrng_cmds	7.350m	23.044ms	50	50	100.00
V2	life cycle	csrng_cmds	7.350m	23.044ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.100m	112.466ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	121.465us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	15.696us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	77.407us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	77.407us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.745us	5	5	100.00
		csrng_csr_rw	5.000s	18.082us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.630us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	215.306us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.745us	5	5	100.00
		csrng_csr_rw	5.000s	18.082us	20	20	100.00
		csrng_csr_aliasing	5.000s	44.630us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	215.306us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	16.000s	76.991us	5	5	100.00
		csrng_tl_intg_err	22.000s	1.901ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	44.006us	50	50	100.00
		csrng_csr_rw	5.000s	18.082us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	5.770ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.100m	112.466ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	5.770ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.100m	112.466ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	5.770ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	22.000s	1.901ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
		csrng_sec_cm	16.000s	76.991us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	1.239ms	200	200	100.00
		csrng_err	17.000s	25.739us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.767m	2.758ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.35	98.39	96.21	99.12	96.76	91.84	100.00	97.32	90.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.28577110210944178518761535605984394102205459623936258485360692348682700024687
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2388969368 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2388969368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.81850466667637312392404567561380673630740452120215357943830004584500757057881
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1507840018 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1507840018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.112863432932332883758987615005882311715818981709949453982785239785148944772698
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1884950649 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1884950649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.51789245485320778294955725464402803237052397853149485640961463631348482014647
    Line 294, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2758128378 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2758128378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

3.csrng_stress_all.66610282302661626447301590873753234540196888123401825831761590779802377722790
Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log

  UVM_ERROR @ 31149880044 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 31149880044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.csrng_stress_all.46110362807700532690107517527738948315599085113503752288038823083992715268182
Line 347, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_stress_all/latest/run.log

  UVM_ERROR @ 1229770570 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1229770570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 7.csrng_stress_all_with_rand_reset.63199826531802012825225231312145814495290924487133354632202796367263252260500
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  39387576 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  39387576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 13.csrng_stress_all.41566296771082365896074478233756112935654151083115832859286738282928110154748
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6779113348 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6779113348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 390.csrng_err.40954036374826323553282471421758812633463138278814358673634149455264861613804
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/390.csrng_err/latest/run.log
```
  UVM_ERROR @  11396659 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11396659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```