CSRNG Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	450.031us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	19.985us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	45.480us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	35.000s	1.415ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	257.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	167.024us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	45.480us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.975us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.333ms	198	200	99.00
V2	alerts	csrng_alert	1.133m	5.162ms	500	500	100.00
V2	err	csrng_err	19.000s	32.225us	500	500	100.00
V2	cmds	csrng_cmds	6.117m	32.473ms	50	50	100.00
V2	life cycle	csrng_cmds	6.117m	32.473ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.833m	121.721ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	187.077us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	51.205us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.225ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.225ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	19.985us	5	5	100.00
		csrng_csr_rw	5.000s	45.480us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.975us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	151.221us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	19.985us	5	5	100.00
		csrng_csr_rw	5.000s	45.480us	20	20	100.00
		csrng_csr_aliasing	9.000s	257.975us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	151.221us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	5.000s	62.405us	5	5	100.00
		csrng_tl_intg_err	17.000s	1.206ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	42.392us	50	50	100.00
		csrng_csr_rw	5.000s	45.480us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	5.162ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.833m	121.721ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	5.162ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.833m	121.721ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	5.162ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	1.206ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
		csrng_sec_cm	5.000s	62.405us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.333ms	198	200	99.00
		csrng_err	19.000s	32.225us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.867m	3.879ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.37	98.39	96.21	99.09	96.81	91.90	100.00	97.32	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.12344703960523571992943337892588559552732559235948490879030406116729140024378
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105607152 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105607152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.54298132843040428420246443289125463104901132196425771669280712723133798158164
    Line 301, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3642123011 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3642123011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

6.csrng_stress_all_with_rand_reset.74665728463805584048853841199933989960742761740664986742036340584062312732293
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  10274205 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  10274205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.csrng_stress_all_with_rand_reset.47645799951279162391325912971722707394900223723540596468241588256583255669791
Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  49206891 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  49206891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

104.csrng_intr.21996197519189513081571950460950703802750445313133754629040932941693710413483
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 94128310 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  94128310 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  94128310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

154.csrng_intr.99791936302473133310938747732488955047554049590419585654331340987669141261260
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/154.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 135220842 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 135220842 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 135220842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 1.csrng_stress_all_with_rand_reset.44546361626788653162349877748607682497180437435300331091710078235427534082869
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3879477430 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3879477430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 5.csrng_stress_all.9115275878412934531776376092220075108012721302761809804048011192980108815517
    Line 372, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3807159519 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3807159519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 8.csrng_stress_all.10736585478201222605918686924902712918481892187980817807553190752526662611295
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1527329610 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1527329610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```