e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | edn_smoke | 1.060s | 181.906us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | edn_csr_hw_reset | 1.040s | 34.006us | 5 | 5 | 100.00 |
V1 | csr_rw | edn_csr_rw | 0.910s | 26.928us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | edn_csr_bit_bash | 5.140s | 359.266us | 5 | 5 | 100.00 |
V1 | csr_aliasing | edn_csr_aliasing | 1.370s | 107.261us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 1.620s | 79.367us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.910s | 26.928us | 20 | 20 | 100.00 |
edn_csr_aliasing | 1.370s | 107.261us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | firmware | edn_genbits | 1.540s | 149.267us | 50 | 50 | 100.00 |
V2 | csrng_commands | edn_genbits | 1.540s | 149.267us | 50 | 50 | 100.00 |
V2 | genbits | edn_genbits | 1.540s | 149.267us | 50 | 50 | 100.00 |
V2 | interrupts | edn_intr | 1.140s | 20.202us | 50 | 50 | 100.00 |
V2 | alerts | edn_alert | 1.060s | 18.611us | 50 | 50 | 100.00 |
V2 | errs | edn_err | 1.170s | 19.411us | 50 | 50 | 100.00 |
V2 | disable | edn_disable | 0.910s | 13.628us | 49 | 50 | 98.00 |
edn_disable_auto_req_mode | 1.180s | 91.044us | 50 | 50 | 100.00 | ||
V2 | stress_all | edn_stress_all | 4.180s | 249.893us | 50 | 50 | 100.00 |
V2 | intr_test | edn_intr_test | 0.890s | 51.018us | 50 | 50 | 100.00 |
V2 | alert_test | edn_alert_test | 1.310s | 44.598us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | edn_tl_errors | 4.730s | 162.510us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | edn_tl_errors | 4.730s | 162.510us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | edn_csr_hw_reset | 1.040s | 34.006us | 5 | 5 | 100.00 |
edn_csr_rw | 0.910s | 26.928us | 20 | 20 | 100.00 | ||
edn_csr_aliasing | 1.370s | 107.261us | 5 | 5 | 100.00 | ||
edn_same_csr_outstanding | 1.490s | 339.643us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | edn_csr_hw_reset | 1.040s | 34.006us | 5 | 5 | 100.00 |
edn_csr_rw | 0.910s | 26.928us | 20 | 20 | 100.00 | ||
edn_csr_aliasing | 1.370s | 107.261us | 5 | 5 | 100.00 | ||
edn_same_csr_outstanding | 1.490s | 339.643us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 489 | 490 | 99.80 | |||
V2S | tl_intg_err | edn_sec_cm | 6.460s | 787.710us | 5 | 5 | 100.00 |
edn_tl_intg_err | 3.120s | 153.182us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | edn_regwen | 0.890s | 17.156us | 10 | 10 | 100.00 |
V2S | sec_cm_config_mubi | edn_alert | 1.060s | 18.611us | 50 | 50 | 100.00 |
V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 6.460s | 787.710us | 5 | 5 | 100.00 |
V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 6.460s | 787.710us | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | edn_sec_cm | 6.460s | 787.710us | 5 | 5 | 100.00 |
V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.060s | 18.611us | 50 | 50 | 100.00 |
edn_sec_cm | 6.460s | 787.710us | 5 | 5 | 100.00 | ||
V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.060s | 18.611us | 50 | 50 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 3.120s | 153.182us | 20 | 20 | 100.00 |
V2S | TOTAL | 35 | 35 | 100.00 | |||
V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 34.815m | 86.854ms | 49 | 50 | 98.00 |
V3 | TOTAL | 49 | 50 | 98.00 | |||
TOTAL | 678 | 680 | 99.71 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 11 | 11 | 10 | 90.91 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.45 | 99.03 | 94.43 | 96.79 | 74.34 | 98.62 | 99.77 | 98.14 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
8.edn_disable.777575467
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_disable/latest/run.log
UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
31.edn_stress_all_with_rand_reset.774079620
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:05c94595-e1d2-47c2-987a-38d84eaecbaf