EDN Simulation Results

Wednesday October 11 2023 19:03:00 UTC

GitHub Revision: f600eccc2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1737291072

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.920s	17.552us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.900s	16.465us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.920s	28.609us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.310s	512.878us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.410s	35.964us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.620s	28.186us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	28.609us	20	20	100.00
		edn_csr_aliasing	1.410s	35.964us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.540s	35.886us	50	50	100.00
V2	csrng_commands	edn_genbits	1.540s	35.886us	50	50	100.00
V2	genbits	edn_genbits	1.540s	35.886us	50	50	100.00
V2	interrupts	edn_intr	1.150s	19.537us	50	50	100.00
V2	alerts	edn_alert	1.050s	94.989us	50	50	100.00
V2	errs	edn_err	1.400s	36.804us	100	100	100.00
V2	disable	edn_disable	0.900s	12.932us	49	50	98.00
		edn_disable_auto_req_mode	1.140s	56.977us	49	50	98.00
V2	stress_all	edn_stress_all	4.000s	404.502us	50	50	100.00
V2	intr_test	edn_intr_test	0.910s	16.560us	50	50	100.00
V2	alert_test	edn_alert_test	1.060s	25.118us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.930s	489.662us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.930s	489.662us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.900s	16.465us	5	5	100.00
		edn_csr_rw	0.920s	28.609us	20	20	100.00
		edn_csr_aliasing	1.410s	35.964us	5	5	100.00
		edn_same_csr_outstanding	1.450s	53.624us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.900s	16.465us	5	5	100.00
		edn_csr_rw	0.920s	28.609us	20	20	100.00
		edn_csr_aliasing	1.410s	35.964us	5	5	100.00
		edn_same_csr_outstanding	1.450s	53.624us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	edn_sec_cm	6.210s	441.133us	5	5	100.00
		edn_tl_intg_err	2.760s	124.884us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.920s	13.784us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	94.989us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.210s	441.133us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.210s	441.133us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.210s	441.133us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	94.989us	50	50	100.00
		edn_sec_cm	6.210s	441.133us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	94.989us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.760s	124.884us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	49.008m	444.658ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			727	730	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.85	99.02	92.26	96.79	94.08	98.62	99.77	97.45

Failure Buckets

• UVM_FATAL (edn_scoreboard.sv:471) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. has 1 failures:

  • Test edn_disable_auto_req_mode has 1 failures.

    • 0.edn_disable_auto_req_mode.2174972824
      Line 215, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @  48915656 ps: (edn_scoreboard.sv:471) [uvm_test_top.env.scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode 0x00000001 exceeded.
        UVM_INFO @  48915656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 32.edn_stress_all_with_rand_reset.4014117032
      Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:bdeb11e0-5a28-4fc0-a4d1-619b23373cba
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test edn_disable has 1 failures.

    • 42.edn_disable.4247882548
      Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/42.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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