EDN Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.920s	15.069us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	17.140us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	55.352us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.390s	436.096us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.140s	59.584us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.590s	22.288us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	55.352us	20	20	100.00
		edn_csr_aliasing	1.140s	59.584us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.700s	410.144us	300	300	100.00
V2	csrng_commands	edn_genbits	3.700s	410.144us	300	300	100.00
V2	genbits	edn_genbits	3.700s	410.144us	300	300	100.00
V2	interrupts	edn_intr	1.150s	20.313us	50	50	100.00
V2	alerts	edn_alert	1.180s	32.405us	50	50	100.00
V2	errs	edn_err	1.550s	19.776us	100	100	100.00
V2	disable	edn_disable	1.000s	68.022us	46	50	92.00
		edn_disable_auto_req_mode	1.420s	116.843us	50	50	100.00
V2	stress_all	edn_stress_all	4.780s	784.903us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	16.621us	50	50	100.00
V2	alert_test	edn_alert_test	1.230s	39.405us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.270s	506.851us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.270s	506.851us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	17.140us	5	5	100.00
		edn_csr_rw	0.960s	55.352us	20	20	100.00
		edn_csr_aliasing	1.140s	59.584us	5	5	100.00
		edn_same_csr_outstanding	1.490s	43.303us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	17.140us	5	5	100.00
		edn_csr_rw	0.960s	55.352us	20	20	100.00
		edn_csr_aliasing	1.140s	59.584us	5	5	100.00
		edn_same_csr_outstanding	1.490s	43.303us	20	20	100.00
V2		TOTAL			786	790	99.49
V2S	tl_intg_err	edn_sec_cm	7.520s	6.504ms	5	5	100.00
		edn_tl_intg_err	3.490s	316.364us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.950s	13.099us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.180s	32.405us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.520s	6.504ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.520s	6.504ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.520s	6.504ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.180s	32.405us	50	50	100.00
		edn_sec_cm	7.520s	6.504ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.180s	32.405us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.490s	316.364us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.286m	432.847ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			975	980	99.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.09	99.02	92.32	96.84	94.08	98.62	99.77	99.00

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_disable has 2 failures.
  - 6.edn_disable.113371066545259129149636314028624595798459902258764879442515287834487287037257
    Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable/latest/run.log
```
  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.edn_disable.111547628722469859773661971821081986167925967161090879552443751097281046134536
    Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_disable/latest/run.log
```
  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (edn_scoreboard.sv:285) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.ctrl has 2 failures:

Test edn_disable has 2 failures.

12.edn_disable.44129053052436375138775148310203661644743270311315972433876260965290690903231
Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/12.edn_disable/latest/run.log

  UVM_ERROR @   1258693 ps: (edn_scoreboard.sv:285) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (39270 [0x9966] vs 39273 [0x9969]) reg name: edn_reg_block.ctrl
  UVM_INFO @   1258693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.edn_disable.28920544474718389854612443914491676621487388619829564699113526408434530623652
Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/19.edn_disable/latest/run.log

  UVM_ERROR @   1595638 ps: (edn_scoreboard.sv:285) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (39270 [0x9966] vs 39273 [0x9969]) reg name: edn_reg_block.ctrl
  UVM_INFO @   1595638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 23.edn_stress_all_with_rand_reset.96946554333797447953923257906017028080828409100075454307820281602201953453503
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c7b2c363-1af0-4e8d-8e7d-57bee1683ba2
```