EDN Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	19.138us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.030s	18.696us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	15.366us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.540s	494.696us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.680s	133.352us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.650s	87.624us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	15.366us	20	20	100.00
		edn_csr_aliasing	1.680s	133.352us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.840s	770.237us	300	300	100.00
V2	csrng_commands	edn_genbits	6.840s	770.237us	300	300	100.00
V2	genbits	edn_genbits	6.840s	770.237us	300	300	100.00
V2	interrupts	edn_intr	1.170s	21.435us	50	50	100.00
V2	alerts	edn_alert	1.610s	468.575us	200	200	100.00
V2	errs	edn_err	1.370s	28.114us	100	100	100.00
V2	disable	edn_disable	1.030s	13.125us	50	50	100.00
		edn_disable_auto_req_mode	1.570s	53.356us	50	50	100.00
V2	stress_all	edn_stress_all	6.380s	563.427us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	13.897us	50	50	100.00
V2	alert_test	edn_alert_test	1.050s	20.320us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.630s	137.559us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.630s	137.559us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.030s	18.696us	5	5	100.00
		edn_csr_rw	0.990s	15.366us	20	20	100.00
		edn_csr_aliasing	1.680s	133.352us	5	5	100.00
		edn_same_csr_outstanding	1.480s	122.172us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.030s	18.696us	5	5	100.00
		edn_csr_rw	0.990s	15.366us	20	20	100.00
		edn_csr_aliasing	1.680s	133.352us	5	5	100.00
		edn_same_csr_outstanding	1.480s	122.172us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	2.490s	512.456us	0	5	0.00
		edn_tl_intg_err	6.200s	1.326ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.000s	17.405us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.610s	468.575us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.490s	512.456us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.490s	512.456us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.490s	512.456us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.490s	512.456us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.610s	468.575us	200	200	100.00
		edn_sec_cm	2.490s	512.456us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.610s	468.575us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.200s	1.326ms	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	35.136m	330.392ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.24	98.25	93.07	91.10	86.05	95.50	96.83	91.89

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.34299359568848372465292589661168344678023408838600054326005816702909329066132
Line 277, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @  16565539 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  16565539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.112218278145925102439245050213842092299037462983064092590867503021885752512192
Line 441, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @ 512456293 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @ 512456293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.