EDN Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	18.174us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.020s	17.361us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	16.466us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.430s	520.809us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.660s	134.753us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	110.958us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	16.466us	20	20	100.00
		edn_csr_aliasing	1.660s	134.753us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.716m	10.390ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.716m	10.390ms	300	300	100.00
V2	genbits	edn_genbits	1.716m	10.390ms	300	300	100.00
V2	interrupts	edn_intr	1.140s	22.051us	50	50	100.00
V2	alerts	edn_alert	1.430s	33.423us	200	200	100.00
V2	errs	edn_err	1.600s	34.079us	100	100	100.00
V2	disable	edn_disable	0.970s	13.387us	50	50	100.00
		edn_disable_auto_req_mode	1.470s	44.120us	50	50	100.00
V2	stress_all	edn_stress_all	6.120s	308.011us	50	50	100.00
V2	intr_test	edn_intr_test	1.040s	25.962us	50	50	100.00
V2	alert_test	edn_alert_test	1.180s	30.505us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.600s	173.725us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.600s	173.725us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.020s	17.361us	5	5	100.00
		edn_csr_rw	0.940s	16.466us	20	20	100.00
		edn_csr_aliasing	1.660s	134.753us	5	5	100.00
		edn_same_csr_outstanding	1.340s	70.227us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.020s	17.361us	5	5	100.00
		edn_csr_rw	0.940s	16.466us	20	20	100.00
		edn_csr_aliasing	1.660s	134.753us	5	5	100.00
		edn_same_csr_outstanding	1.340s	70.227us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	1.950s	254.144us	0	5	0.00
		edn_tl_intg_err	2.740s	111.727us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	18.827us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.430s	33.423us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	1.950s	254.144us	0	5	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	1.950s	254.144us	0	5	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	1.950s	254.144us	0	5	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	1.950s	254.144us	0	5	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.430s	33.423us	200	200	100.00
		edn_sec_cm	1.950s	254.144us	0	5	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.430s	33.423us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.740s	111.727us	20	20	100.00
V2S		TOTAL			30	35	85.71
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.748m	532.071ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1125	1130	99.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.17	98.25	93.07	90.85	87.21	95.50	96.83	90.48

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: edn_reg_block.main_sm_state reset value: *

has 5 failures:

Test edn_sec_cm has 5 failures.

0.edn_sec_cm.17383554452326439768491388175437662441472009294850224914424196104493921272307
Line 356, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log

  UVM_ERROR @  26837400 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  26837400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_sec_cm.80208304431116531673612220686185858024955207583037575091189719435602859134371
Line 304, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest/run.log

  UVM_ERROR @  11470658 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (193 [0xc1] vs 382 [0x17e]) Regname: edn_reg_block.main_sm_state reset value: 0xc1
  UVM_INFO @  11470658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.